Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 577
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.2.2.2 H_CSR—Host Control Status Register (Intel
®
MEI 2 MMIO Register)
Address Offset: MEI1_MBAR + 04h Attribute: RO, R/W, R/WC
Default Value: 02000000h Size: 32 bits
17.2.2.3 ME_CB_RW—Intel
®
ME Circular Buffer Read Window Register
(Intel
®
MEI 2 MMIO Register)
Address Offset: MEI1_MBAR + 08h Attribute: RO
Default Value: FFFFFFFFh Size: 32 bits
17.2.2.4 ME_CSR_HA—Intel
®
ME Control Status Host Access Register
(Intel
®
MEI 2 MMIO Register)
Address Offset: MEI1_MBAR + 0Ch Attribute: RO
Default Value: 02000000h Size: 32 bits
Bit Description
31:24 Host Circular Buffer Depth (H_CBD) — RO. This field indicates the maximum number of 32 bit
entries available in the host circular buffer (H_CB). Host software uses this field along with the
H_CBRP and H_CBWP fields to calculate the number of valid entries in the H_CB to read or # of
entries available for write.
This field is implemented with a “1-hot” scheme. Only one bit will be set to a “1” at a time. Each bit
position represents the value n of a buffer depth of (2^n). For example, when bit# 1 is 1, the buffer
depth is 2; when bit#2 is 1, the buffer depth is 4, etc. The allowed buffer depth values are 2, 4, 8,
16, 32, 64 and 128.
23:16
Host CB Write Pointer (H_CBWP) — RO. Points to next location in the H_CB for host to write the
data. Software uses this field along with H_CBRP and H_CBD fields to calculate the number of valid
entries in the H_CB to read or number of entries available for write.
15:8
Host CB Read Pointer (H_CBRP) — RO. Points to next location in the H_CB where a valid data is
available for embedded controller to read. Software uses this field along with H_CBWR and H_CBD
fields to calculate the number of valid entries in the host CB to read or number of entries available
for write.
7:5
Reserved
Note: For writes to this register, these bits shall be written as 000b.
4
Host Reset (H_RST) — R/W. Setting this bit to 1 will initiate a Intel MEI reset sequence to get the
circular buffers into a known good state for host and Intel ME communication. When this bit
transitions from 0 to 1, hardware will clear the H_RDY and ME_RDY bits.
3
Host Ready (H_RDY) — R/W. This bit indicates that the host is ready to process messages.
2
Host Interrupt Generate (H_IG) — R/W. Once message(s) are written into its CB, the host sets
this bit to one for the HW to set the ME_IS bit in the ME_CSR and to generate an interrupt message
to Intel ME. HW will send the interrupt message to Intel ME only if the ME_IE is enabled. HW then
clears this bit to 0.
1
Host Interrupt Status (H_IS) — R/WC. Hardware sets this bit to 1 when ME_IG bit is set to 1.
Host clears this bit to 0 by writing a 1 to this bit position. H_IE has no effect on this bit.
0
Host Interrupt Enable (H_IE) — R/W. Host sets this bit to 1 to enable the host interrupt (INTR#
or MSI) to be asserted when H_IS is set to 1.
Bit Description
31:0 Intel ME Circular Buffer Read Window Field (ME_CB_RWF). This bit field is for host to read
from the Intel ME Circular Buffer. The Intel ME's circular buffer is located at the Intel ME subsystem
address specified in the Intel ME CB Base Address register. This field is read only, writes have no
effect. Reads to this register will increment the ME_CBRP as long as ME_RDY is 1. When ME_RDY is
0, reads to this register have no effect, all 1s are returned, and ME_CBRP is not incremented.
Bit Description
31:24 Intel ME Circular Buffer Depth Host Read Access (ME_CBD_HRA).
Host read only access to ME_CBD.
23:16 Intel ME CB Write Pointer Host Read Access (ME_CBWP_HRA).
Host read only access to ME_CBWP.