Datasheet
Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 575
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.2.1.21 MA—Message Signaled Interrupt Message Address Register
(Intel
®
MEI 2—D22:F1)
Address Offset: 90h–93h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
17.2.1.22 MUA—Message Signaled Interrupt Upper Address Register
(Intel
®
MEI 2—D22:F1)
Address Offset: 94h–97h Attribute: R/W
Default Value: 00000000h Size: 32 bits
17.2.1.23 MD—Message Signaled Interrupt Message Data
Register (Intel
®
MEI 2—D22:F1)
Address Offset: 98h–99h Attribute: R/W
Default Value: 0000h Size: 16 bits
17.2.1.24 HIDM—Intel
®
MEI Interrupt Delivery Mode Register (Intel
®
MEI 2—
D22:F1)
Address Offset: A0h Attribute: R/W
Default Value: 00h Size: 8 bits
17.2.1.25 HERES—Intel
®
MEI Extend Register Status (Intel
®
MEI 2—D22:F1)
Address Offset: BCh–BFh Attribute: RO
Default Value: Size: 32 bits
Bit Description
31:2 Address (ADDR) — R/W. Lower 32 bits of the system specified message address, always DW
aligned.
1:0 Reserved
Bit Description
31:0 Upper Address (UADDR) — R/W. Upper 32 bits of the system specified message address, always
DW aligned.
Bit Description
15:0 Data (DATA) — R/W. This 16-bit field is programmed by system software if MSI is enabled. Its
content is driven during the data phase of the MSI memory write transaction.
Bit Description
7:2 Reserved
1:0 Intel MEI Interrupt Delivery Mode (HIDM) — R/W. These bits control what type of interrupt the
Intel MEI will send the host. They are interpreted as follows:
00 = Generate Legacy or MSI interrupt
01 = Generate SCI
10 = Generate SMI
Bit Description
31 Extend Register Valid (ERV)- RO. Set by firmware after all firmware has been loaded. If ERA field
is SHA-1, the result of the extend operation is in HER:5-1. If ERA field is SHA-256, the result of the
extend operation is in HER:8-1.
30 Extend Feature Present (EFP)- RO. This bit is hardwired to 1 to allow driver software to easily
detect the chipset supports the Extend Register FW measurement feature.
29:4 Reserved