Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
574 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.2.1.18 PMCS—PCI Power Management Control and Status Register
(Intel
®
MEI 2—D22:F1)
Address Offset: 54h–55h Attribute: R/WC, R/W, RO
Default Value: 0008h Size: 16 bits
17.2.1.19 MID—Message Signaled Interrupt Identifiers Register (Intel
®
MEI 2—
D22:F1)
Address Offset: 8Ch-8Dh Attribute: RO
Default Value: 0005h Size: 16 bits
17.2.1.20 MC—Message Signaled Interrupt Message Control Register
(Intel
®
MEI 2—D22:F1)
Address Offset: 8Eh–8Fh Attribute: R/W, RO
Default Value: 0080h Size: 16 bits
Bit Description
15 PME Status (PMES) — R/WC. Bit is set by Intel Server Platform Services FW. Host software clears
bit by writing 1 to bit.
This bit is reset when CL_RST# is asserted.
14:9 Reserved
8 PME Enable (PMEE) — R/W. This bit is read/write and is under the control of host SW. It does not
directly have an effect on PME events. However, this bit is shadowed so Intel SPS FW can monitor it.
Intel SPS FW will not cause the PMES bit to transition to 1 while the PMEE bit is 0, indicating that
host SW had disabled PME.
This bit is reset when PLTRST# asserted.
7:4 Reserved
3 No_Soft_Reset (NSR) — RO. This bit indicates that when the Intel MEI host controller is
transitioning from D3
hot
to D0 due to a power state command, it does not perform an internal reset.
Configuration context is preserved.
2 Reserved
1:0 Power State (PS) — R/W. This field is used both to determine the current power state of the Intel
MEI host controller and to set a new power state. The values are:
00 = D0 state (default)
11 = D3
hot
state
The D1 and D2 states are not supported for the Intel MEI host controller. When in the D3
hot
state,
the Intel ME’s configuration space is available, but the register memory spaces are not. Additionally,
interrupts are blocked.
Bit Description
15:8 Next Pointer (NEXT) — RO. Value of 00h indicates that this is the last item in the list.
7:0 Capability ID (CID) — RO. Capabilities ID indicates MSI.
Bit Description
15:8 Reserved
7 64 Bit Address Capable (C64) — RO. Specifies that function is capable of generating 64-bit
messages.
6:1 Reserved
0 MSI Enable (MSIE) — R/W. If set, MSI is enabled and traditional interrupt pins are not used to
generate interrupts.