Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 573
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.2.1.14 GMES—General Intel
®
ME Status Register (Intel
®
MEI 2—D22:F1)
Address Offset: 48h–4Bh Attribute: RO
Default Value: 00000000h Size: 32 bits
17.2.1.15 H_GS—Host General Status Register (Intel
®
MEI 2—D22:F1)
Address Offset: 4Ch–4Fh Attribute: R/W
Default Value: 00000000h Size: 32 bits
17.2.1.16 PID—PCI Power Management Capability ID Register (Intel
®
MEI 2—
D22:F1)
Address Offset: 50h–51h Attribute: RO
Default Value: 8C01h Size: 16 bits
17.2.1.17 PC—PCI Power Management Capabilities Register (Intel
®
MEI 2—
D22:F1)
Address Offset: 52h–53h Attribute: RO
Default Value: C803h Size: 16 bits
7:1 Cores Disabled: The number of physical processor cores that should be disabled on each processor
socket.
NOTE: These bits are valid only if bit 31 ‘NM Enabled’ is set.
0 BIOS Booting Mode: This bit is controlled by NM boot time policy. Two modes are supported:
0 – BIOS should run in power optimized mode.
1 –BIOS should run in performance optimized mode (this is the default value when NM is enabled
and there is no boot time policy set).
NOTE: This bit is valid only if bit 31 ‘Intel
®
NM Enabled’ is set.
Bit Description
Bit Description
31:24 PTSeqNo: P/T-state limit request sequence number.
23:0 Reserved
Bit Description
31:24 PTSeqNo: P/T-state limit request sequence number.
23:0 Reserved
Bit Description
15:8 Next Capability (NEXT) — RO. Value of 8Ch indicates the location of the next pointer.
7:0 Capability ID (CID) — RO. Indicates the linked list item is a PCI Power Management Register.
Bit Description
15:11 PME_Support (PSUP) — RO. This five-bit field indicates the power states in which the function
may assert PME#. Intel MEI can assert PME# from any D-state except D1 or D2 which are not
supported by Intel MEI.
10:9 Reserved
8:6 Aux_Current (AC) — RO. Reports the maximum Suspend well current required when in the D3
cold
state. Value of 00b is reported.
5 Device Specific Initialization (DSI) — RO. Indicates whether device-specific initialization is
required.
4Reserved
3 PME Clock (PMEC) — RO. Indicates that PCI clock is not required to generate PME#.
2:0 Version (VS) — RO. Hardwired to 011b to indicate support for Revision 1.2 of the PCI Power
Management Specification.