Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
572 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.2.1.9 SVID—Subsystem Vendor ID Register (Intel
®
MEI 2—D22:F1)
Address Offset: 2Ch–2Dh Attribute: R/WO
Default Value: 0000h Size: 16 bits
17.2.1.10 SID—Subsystem ID Register (Intel
®
MEI 2—D22:F1)
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 0000h Size: 16 bits
17.2.1.11 CAPP—Capabilities List Pointer Register (Intel
®
MEI 2—D22:F1)
Address Offset: 34h Attribute: RO
Default Value: 50h Size: 8 bits
17.2.1.12 INTR—Interrupt Information Register (Intel
®
MEI 2—D22:F1)
Address Offset: 3Ch–3Dh Attribute: R/W, RO
Default Value: 0200h Size: 16 bits
17.2.1.13 HFS—Host Firmware Status Register (Intel
®
MEI 2—D22:F1)
Address Offset: 40h–43h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
15:0 Subsystem Vendor ID (SSVID) — R/WO. Indicates the sub-system vendor identifier. This field
should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This
field can only be cleared by PLTRST#.
Note: Register must be written as a Word write or as a DWord write with SID register.
Bit Description
15:0 Subsystem ID (SSID) — R/WO. Indicates the sub-system identifier. This field should be
programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can
only be cleared by PLTRST#.
Note: Register must be written as a Word write or as a DWord write with SVID register.
Bit Description
7:0 Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the capabilities
list is at 50h in configuration space.
Bit Description
15:8 Interrupt Pin (IPIN) — RO. This field indicates the interrupt pin the Intel MEI host controller uses.
A value of 1h/2h/3h/4h indicates that this function implements legacy interrupt on INTA/INTB/INTC/
INTD, respectively.
7:0 Interrupt Line (ILINE) — R/W. Software written value to indicate which interrupt line (vector) the
interrupt is connected to. No hardware action is taken on this register.
Bit Description
31 Intel
®
NM Enabled: Node Manager power management enabled.
30:12 Reserved
11:9 SmaRT & CLST Status:
bit 9 – Under-voltage event was noticed at least once since last Intel
®
ME reset
bit 10 – Over-current event was noticed at least once since last Intel
®
ME reset
bit 11 – Over-temperature event was noticed at least once since last Intel
®
ME reset
NOTE: These bits are valid only if bit 31 ‘NM Enabled’ is set.
8 Power Limiting: If set to ‘1’ Intel
®
ME is actively limiting platform power consumption.
NOTE: This bit is valid only if bit 31 ‘NM Enabled’ is set
.