Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
570 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.2.1.1 VID—Vendor Identification Register (Intel
®
MEI 2—D22:F1)
Address Offset: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
17.2.1.2 DID—Device Identification Register (Intel
®
MEI 2—D22:F1)
Address Offset: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bits
17.2.1.3 PCICMD—PCI Command Register (Intel
®
MEI 2—D22:F1)
Address Offset: 04h–05h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
17.2.1.4 PCISTS—PCI Status Register (Intel
®
MEI 2—D22:F1)
Address Offset: 06h–07h Attribute: RO
Default Value: 0010h Size: 16 bits
A0h HIDM Intel MEI Interrupt Delivery Mode 00h R/W
BC–BFh HERES Intel MEI Extended Register Status 40000000h RO
C0–DFh HER[1:8] Intel MEI Extended Register DW[1:8] 00000000h RO
Table 17-3. Intel
®
MEI 2 Configuration Registers Address Map (Intel
®
MEI 2—D22:F1)
(Sheet 2 of 2)
Offset Mnemonic Register Name Default Attribute
Bit Description
15:0 Vendor ID (VID) — RO. This is a 16-bit value assigned to Intel.
Bit Description
15:0 Device ID (DID) — RO. This is a 16-bit value assigned to the Intel ME Interface controller. See the
Specification Update for the value of the DID Register.
Bit Description
15:11 Reserved
10 Interrupt Disable (ID) — R/W. Disables this device from generating PCI line based interrupts. This
bit does not have any effect on MSI operation.
9:3 Reserved
2 Bus Master Enable (BME)— R/W. Controls the Intel MEI host controller's ability to act as a system
memory master for data transfers. When this bit is cleared, Intel MEI bus master activity stops and
any active DMA engines return to an idle condition. This bit is made visible to firmware through the
H_PCI_CSR register, and changes to this bit may be configured by the H_PCI_CSR register to
generate an Intel ME MSI. When this bit is 0, Intel MEI is blocked from generating MSI to the host
processor.
Note: This bit does not block Intel MEI accesses to Intel ME UMA; that is, writes or reads to the
host and Intel ME circular buffers through the read window and write window registers still
cause Intel ME backbone transactions to Intel ME UMA.
1 Memory Space Enable (MSE) — R/W. Controls access to the Intel ME's memory mapped register
space.
0 = Disable. Memory cycles within the range specified by the memory base and limit registers are
master aborted.
1 = Enable. Allows memory cycles within the range specified by the memory base and limit registers
accepted.
0Reserved
Bit Description
15:5 Reserved