Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 57
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.3.1.1 Transaction Layer
The upper layer of the host architecture is the transaction layer. The transaction layer
connects to the device GbE controller using an implementation specific protocol.
Through this GbE controller-to-transaction-layer protocol, the application-specific parts
of the device interact with the subsystem and transmit and receive requests to or from
the remote agent, respectively.
3.3.1.2 Data Alignment
3.3.1.2.1 4-KB Boundary
PCI requests must never specify an address/length combination that causes a memory
space access to cross a 4 KB boundary. It is hardware’s responsibility to break requests
into 4 KB-aligned requests (if needed). This does not pose any requirement on
software. However, if software allocates a buffer across a 4-KB boundary, hardware
issues multiple requests for the buffer. Software should consider aligning buffers to a
4-KB boundary in cases where it improves performance.
The alignment to the 4-KB boundaries is done by the GbE controller. The transaction
layer does not do any alignment according to these boundaries.
3.3.1.2.2 64 Bytes
PCI requests are 128 bytes or less and are aligned to make better use of memory
controller resources. Writes, however, can be on any boundary and can cross a 64-byte
alignment boundary.
3.3.1.3 Configuration Request Retry Status
The integrated GbE controller might have a delay in initialization due to an NVM read. If
the NVM configuration read operation is not completed and the device receives a
configuration request, the device responds with a configuration request retry
completion status to terminate the request, and thus effectively stalls the configuration
request until such
time that the sub-system has completed local initialization and is ready to
communicate with the host.
3.3.2 Error Events and Error Reporting
3.3.2.1 Data Parity Error
The PCI host bus does not provide parity protection, but it does forward parity errors
from bridges. The integrated GbE controller recognizes parity errors through the
internal bus interface and sets the Parity Error bit in PCI configuration space. If parity
errors are enabled in configuration space, a system error is indicated on the PCI host
bus. The offending cycle with a parity error is dropped and not processed by the
integrated GbE controller.
3.3.2.2 Completion with Unsuccessful Completion Status
A completion with unsuccessful completion status (any status other than 000) is
dropped and not processed by the integrated GbE controller. Furthermore, the request
that corresponds to the unsuccessful completion is not retried. When this unsuccessful