Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 567
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.1.2 MEI0_MBAR—Intel
®
MEI 1 MMIO Registers
These MMIO registers are accessible starting at the Intel MEI 1 MMIO Base Address
(MEI0_MBAR) which gets programmed into D22:F0:Offset 10–17h. These registers are
reset by PLTRST# unless otherwise noted.
17.1.2.1 H_CB_WW—Host Circular Buffer Write Window Register
(Intel
®
MEI 1 MMIO Register)
Address Offset: MEI0_MBAR + 00h Attribute: W
Default Value: 00000000h Size: 32 bits
17.1.2.2 H_CSR—Host Control Status Register (Intel
®
MEI 1 MMIO Register)
Address Offset: MEI0_MBAR + 04h Attribute: RO, R/W, R/WC
Default Value: 02000000h Size: 32 bits
Table 17-2. Intel
®
MEI 1 MMIO Register Address Map
MEI0_MBAR+Of
fset
Mnemonic Register Name Default Attribute
00–03h H_CB_WW Host Circular Buffer Write Window 00000000h W
04h–07h H_CSR Host Control Status 02000000h RO, R/W,
R/WC
08h–0Bh ME_CB_RW Intel ME Circular Buffer Read Window FFFFFFFFh RO
0Ch–0Fh ME_CSR_HA Intel ME Control Status Host Access 02000000h RO
Bit Description
31:0 Host Circular Buffer Write Window Field (H_CB_WWF). This bit field is for host to write into its
circular buffer. The host's circular buffer is located at the Intel ME subsystem address specified in the
Host CB Base Address register. This field is write only, reads will return arbitrary data. Writes to this
register will increment the H_CBWP as long as ME_RDY is 1. When ME_RDY is 0, writes to this
register have no effect and are not delivered to the H_CB, nor is H_CBWP incriminated.
Bit Description
31:24 Host Circular Buffer Depth (H_CBD) — RO. This field indicates the maximum number of 32 bit
entries available in the host circular buffer (H_CB). Host software uses this field along with the
H_CBRP and H_CBWP fields to calculate the number of valid entries in the H_CB to read or # of
entries available for write.
This field is implemented with a "1-hot" scheme. Only one bit will be set to a "1" at a time. Each bit
position represents the value n of a buffer depth of (2^n). For example, when bit# 1 is 1, the buffer
depth is 2; when bit#2 is 1, the buffer depth is 4, etc. The allowed buffer depth values are 2, 4, 8,
16, 32, 64 and 128.
23:16
Host CB Write Pointer (H_CBWP) — RO. Points to next location in the H_CB for host to write the
data. Software uses this field along with H_CBRP and H_CBD fields to calculate the number of valid
entries in the H_CB to read or number of entries available for write.
15:8
Host CB Read Pointer (H_CBRP) — RO. Points to next location in the H_CB where a valid data is
available for embedded controller to read. Software uses this field along with H_CBWR and H_CBD
fields to calculate the number of valid entries in the host CB to read or number of entries available
for write.
7:5
Reserved
Note: For writes to this register, these bits shall be written as 000b.
4
Host Reset (H_RST) — R/W. Setting this bit to 1 will initiate a Intel MEI reset sequence to get the
circular buffers into a known good state for host and Intel ME communication. When this bit
transitions from 0 to 1, hardware will clear the H_RDY and ME_RDY bits.
3
Host Ready (H_RDY) — R/W. This bit indicates that the host is ready to process messages.
2
Host Interrupt Generate (H_IG) — R/W. Once message(s) are written into its CB, the host sets
this bit to one for the HW to set the ME_IS bit in the ME_CSR and to generate an interrupt message
to Intel ME. HW will send the interrupt message to Intel ME only if the ME_IE is enabled. HW then
clears this bit to 0.