Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 565
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.1.1.25 H_GS3—Host General Status Register 3 (Intel
®
MEI 1—D22:F0)
Address Offset: 74h–77h Attribute: R/W
Default Value: 00000000h Size: 32 bits
17.1.1.26 MID—Message Signaled Interrupt Identifiers Register (Intel
®
MEI 1—
D22:F0)
Address Offset: 8Ch-8Dh Attribute: RO
Default Value: 0005h Size: 16 bits
17.1.1.27 MC—Message Signaled Interrupt Message Control Register
(Intel
®
MEI 1—D22:F0)
Address Offset: 8Eh–8Fh Attribute: R/W, RO
Default Value: 0080h Size: 16 bits
17.1.1.28 MA—Message Signaled Interrupt Message Address Register
(Intel
®
MEI 1—D22:F0)
Address Offset: 90h–93h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
17.1.1.29 MUA—Message Signaled Interrupt Upper Address Register
(Intel
®
MEI 1—D22:F0)
Address Offset: 94h–97h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 Host General Status 3 (H_GS3)— R/W. General Status of Host, this field is not used by Hardware
Bit Description
15:8 Next Pointer (NEXT) — RO. Value of 00h indicates that this is the last item in the list.
7:0 Capability ID (CID) — RO. Capabilities ID indicates MSI.
Bit Description
15:8 Reserved
7 64 Bit Address Capable (C64) — RO. Specifies that function is capable of generating 64-bit
messages.
6:1 Reserved
0 MSI Enable (MSIE) — R/W. If set, MSI is enabled and traditional interrupt pins are not used to
generate interrupts.
Bit Description
31:2 Address (ADDR) — R/W. Lower 32 bits of the system specified message address, always DW
aligned.
1:0 Reserved
Bit Description
31:0 Upper Address (UADDR) — R/W. Upper 32 bits of the system specified message address, always
DW aligned.