Datasheet
Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 563
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.1.1.16 H_GS—Host General Status Register (Intel
®
MEI 1—D22:F0)
Address Offset: 4Ch–4Fh Attribute: R/W
Default Value: 00000000h Size: 32 bits
17.1.1.17 PID—PCI Power Management Capability ID Register (Intel
®
MEI 1—
D22:F0)
Address Offset: 50h–51h Attribute: RO
Default Value: 8C01h Size: 16 bits
17.1.1.18 PC—PCI Power Management Capabilities Register (Intel
®
MEI 1—
D22:F0)
Address Offset: 52h–53h Attribute: RO
Default Value: C803h Size: 16 bits
17.1.1.19 PMCS—PCI Power Management Control and Status Register
(Intel
®
MEI 1—D22:F0)
Address Offset: 54h–55h Attribute: R/WC, R/W, RO
Default Value: 0008h Size: 16 bits
Bit Description
31:28
Command: Command code.
27:0 Data: Command specific data.
Bit Description
15:8 Next Capability (NEXT) — RO. Value of 8Ch indicates the location of the next pointer.
7:0 Capability ID (CID) — RO. Indicates the linked list item is a PCI Power Management Register.
Bit Description
15:11 PME_Support (PSUP) — RO. This five-bit field indicates the power states in which the function
may assert PME#. Intel MEI can assert PME# from any D-state except D1 or D2 which are not
supported by Intel MEI.
10:9 Reserved
8:6 Aux_Current (AC) — RO. Reports the maximum Suspend well current required when in the D3
cold
state. Value of 00b is reported.
5 Device Specific Initialization (DSI) — RO. Indicates whether device-specific initialization is
required.
4Reserved
3 PME Clock (PMEC) — RO. Indicates that PCI clock is not required to generate PME#.
2:0 Version (VS) — RO. Hardwired to 011b to indicate support for Revision 1.2 of the PCI Power
Management Specification.
Bit Description
15 PME Status (PMES) — R/WC. Bit is set by Intel Server Platform Services Firmware. Host software
clears bit by writing ‘1’ to bit.
This bit is reset when CL_RST# asserted.
14:9 Reserved
8 PME Enable (PMEE) — R/W. This bit is read/write and is under the control of host SW. It does not
directly have an effect on PME events. However, this bit is shadowed so Intel SPS FW can monitor it.
Intel SPS FW will not cause the PMES bit to transition to 1 while the PMEE bit is 0, indicating that
host SW had disabled PME.
This bit is reset when PLTRST# asserted.
7:4 Reserved