Datasheet

Functional Description
56 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
— VLAN support compliant with the 802.3q specification
— MAC address filters: perfect match unicast filters; multicast hash filtering,
broadcast filter and promiscuous mode
— PCI Express/SMBus interface to GbE PHYs
• Host Interface Features
— 64-bit address master support for systems using more than 4 GB of
physical memory
— Programmable host memory receive buffers (256 Bytes to 16 KB)
— Intelligent interrupt generation features to enhance driver performance
— Descriptor ring management hardware for transmit and receive
— Software controlled reset (resets everything except the configuration space)
— Message Signaled Interrupts
• Performance Features
— Configurable receive and transmit data FIFO, programmable in 1 KB increments
— TCP segmentation capability compatible with Windows NT* 5.x off loading
features
— Fragmented UDP checksum offload for packet reassembly
— IPv4 and IPv6 checksum offload support (receive, transmit, and TCP
segmentation offload)
— Split header support to eliminate payload copy from user space to host space
— Receive Side Scaling (RSS) with two hardware receive queues
— Supports 9018 bytes of jumbo packets
— Packet buffer size
— LinkSec offload compliant with 802.3ae specification
— TimeSync offload compliant with 802.1as specification
• Virtualization Technology Features
— Warm function reset – function level reset (FLR)
—VMDq1
• Power Management Features
— Magic Packet* wake-up enable with unique MAC address
— ACPI register set and power down functionality supporting D0 and D3 states
— Full wake up support (APM, ACPI)
— MAC power down at Sx, DMoff with and without WoL
— Auto connect battery saver at S0 no link and Sx no link
— Energy Efficient Ethernet (EEE) support
— Latency Tolerance Reporting (LTR)
— ARP and ND proxy support through LAN Connected Device proxy
3.3.1 GbE PCI Express* Bus Interface
The GbE controller has a PCI Express interface to the host processor and host memory.
The following sections detail the bus transactions.