Datasheet

Thermal Sensor Registers (D31:F6)
556 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
16.2.14 TSPIEN — PCI Interrupt Event Enables Register
Offset Address: TBARB+82h Attribute: RO, R/W
Default Value: 00h Size: 8 bit
16.2.15 TSGPEN—General Purpose Event Enables Register
Offset Address: TBARB+84h Attribute: RO, R/W
Default Value: 00h Size: 8 bit
1 Alert High-to-Low Event (AHLE) — R/WC.
1 = Indicates that a Hot Thermal Sensor trip event occurred based on a lower to higher
temperature transition thru the trip point.
0 = No trip for this event
Software must write a 1 to clear this status bit.
0 Alert Low-to-High Event (ALHE) — R/WC.
1 = Indicates that an Aux Thermal Sensor trip event occurred based on a lower to higher
temperature transition thru the trip point.
0 = No trip for this event
Software must write a 1 to clear this status bit.
Note: AHLE will not be set until there has been one occurrence of a Low to High event (ALHE
must have been set once). This prevents the case where the system power up at a
reasonably high temperature and starts to cool off while booting and causing an interrupt
before there is SW loaded to handle it.
Bit Description
Bit Description
7:2 Reserved
1 Alert High-to-Low Enable — R/W. When set to 1, the thermal sensor logic asserts the Thermal
logic PCI INTx signal when the corresponding status bit is set in the Thermal Error Status register.
When cleared, the corresponding status bit does not result in PCI INTx.
0 Alert Low-to-High Enable — R/W. See the description for bit 1
Bit Description
7:2 Reserved
1 Alert High-to-Low Enable — R/W. When set to 1, the thermal sensor logic asserts its General
Purpose Event signal to the GPE block when the corresponding status bit is set in the Thermal Error
Status register. When cleared, the corresponding status bit does not result in the GPE signal
assertion.
Alert Low-to-High Enable — R/W. See the description for bit 1.