Datasheet

Thermal Sensor Registers (D31:F6)
554 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
16.2.6 TSMIC—Thermal Sensor SMI Control Register
Offset Address: TBARB+0Ch Attribute: RO, R/W
Default Value: 00h Size: 8 bit
16.2.7 CTT—Catastrophic Trip Point Register
Offset Address: TBARB+10h Attribute: RO, R/W
Default Value: 01FFh Size: 16 bit
16.2.8 TAHV—Thermal Alert High Value Register
Offset Address: TBARB+14h Attribute: RO, R/W
Default Value: 0000h Size: 16 bit
16.2.9 TALV—Thermal Alert Low Value Register
Offset Address: TBARB+18h Attribute: R/W, RO
Default Value: 0000h Size: 16 bit
16.2.10 TL—Throttle Levels Register
Offset Address: TBARB+40h Attribute: RO, R/W
Default Value: 00000000h Size: 32 bit
Bit Description
7 Policy Lock-Down Bit — R/W. When written to 1, this bit prevents anymore writes to this register.
6:1 Reserved
0 SMI Enable on Alert Thermal Sensor Trip — R/W.
1 = Enables SMI# assertions on alert thermal sensor events for either low-to-high or high-to-low
events. Both edges are enabled by this one bit.
0 = Disables SMI# assertions for alert thermal events.
Bit Description
15:9 Reserved
8:0 Catastrophic Temperature TRIP (CTRIP) — R/W. When the current temperature reading is
greater than or equal to the value in this register, a catastrophic trip event is signaled.
This register is locked by TSC[7]
Bit Description
15:9 Reserved
8:0 Alert High (AH) — R/W. Sets the high value for the alert indication. See the later section for
usage.
Note: It is illegal for SW to program AH to a value less than TALV.AL.
This register is not lockable, so that SW can change the values during runtime.
Bit Description
15:9 Reserved
8:0 Alert Low (AL) — R/W. Sets the low value for the alert indication. See the later section for usage.
This register is not lockable, so that SW can change the values during runtime.
Bit Description
31 TT.Lock – R/W. When set to ‘1’, this entire register (TL) is locked and remains locked until the next
platform reset.
30 TT.State13 Enable (TT13EN) – R/W. When set to ‘1’ and the programmed GPIO pin is a ‘1’, then
PMSync state 13 will force at least T2 state.