Datasheet

Thermal Sensor Registers (D31:F6)
Intel® Xeon® Processor D-1500 Product Family 553
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
16.2.3 TSS—Thermal Sensor Status Register
Offset Address: TBARB+06h Attribute: RO, R/W
Default Value: 00h Size: 8 bit
This register provides statuses of the thermal sensor.
16.2.4 TSEL — Thermal Sensor Enable and Lock Register
Offset Address: TBARB+08h Attribute: RO, R/W
Default Value: 00h Size: 8 bit
This register controls the operation of the thermal sensor.
16.2.5 TSREL—Thermal Sensor Reporting Enable and Lock
Register
Offset Address: TBARB+0Ah Attribute: RO, R/W
Default Value: 00h Size: 8 bit
Bit Description
7:5 Reserved
4 Thermal Sensor Dynamic Shutdown Status (TSDSS) — RO. This bit indicates the status of the
thermal sensor circuit when TSEL.ETS=1.
1 = thermal sensor is fully operational
0 = thermal sensor is in a dynamic shutdown state
3 GPE Status (GPES) — R/WC. Set when GPE is enabled for a trip event. Software must write a ‘1’
to this bit to clear the GPE status. GPE can be configured to cause an SMI or SCI.
As long as this bit is set, the GPE indication to the global GPE logic is asserted.
2 SMI Status (SMIS) — R/WC. Set when SMI is enabled for a trip event. Software must write a ‘1’
to this bit to clear the SMI status.
As long as this bit is set, the SMI indication to the global SMI logic is asserted.
1:0 Reserved
Bit Description
7 Policy Lock-Down Bit — R/W. When written to 1, this bit prevents any more writes to this
register.
6:1 Reserved
0 Enable TS (ETS) — R/W.
1 = Enables the thermal sensor. Until this bit is set, no thermometer readings or trip events will
occur. If SW reads the TEMP register before the sensor is enabled, it will read 0x0. The value of
this bit is sent to the thermal sensor. NOTE: if the sensor is running and valid temperatures
have been captured in TEMP and then ETS is cleared, TEMP will retain its old value. Clearing
ETS does not force TEMP to 0x00.
0 = Disables the sensor.
Bit Description
7 Policy Lock-Down Bit — R/W. When written to 1, this bit prevents anymore writes to this register.
6:1 Reserved
0 Enable SMBus Temperature Reporting— R/W.
1 = Enables the reporting of Intel® Xeon® Processor D-1500 Product Family temperature to the
SMBus and PMC. This must also be set if ME needs access to Intel® Xeon® Processor D-1500
Product Family temperature. Once enabled this bit should not be cleared by software. If it is
cleared then the EC may get an undefined value. Software has no need to dynamically disable
and then re-enable this bit.
0 = Disables temperature reporting.