Datasheet
Thermal Sensor Registers (D31:F6)
552 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
16.2.1 TEMP—Temperature Register
Offset Address: TBARB+00h Attribute: RO
Default Value: 0000h Size: 16 bit
16.2.2 TSC—Thermal Sensor Control Register
Offset Address: TBARB+04h Attribute: RO, R/W
Default Value: 00h Size: 8 bit
This register controls the operation of the thermal sensor.
Table 16-2. Thermal Memory Mapped Configuration Register Address Map
Offset Mnemonic Register Name Default Attribute
00h–01h TEMP Temperature 0000h RO
04h TSC Thermal Sensor Control 00h RO, R/W
06h TSS Thermal Sensor Status 00h RO, R/W,
R/WC
08h TSEL Thermal Sensor Enable and Lock 00h RO, R/W
0Ah TSREL Thermal Sensor Report Enable and Lock 00h RO, R/W
0Ch TSMIC Thermal Sensor SMI Control 00h RO, R/W
10h–11h CTT Catastrophic Trip Point 01FFh RO, R/W
14h–15h TAHV Thermal Alert High Value 0000h RO, R/W
18h–19h TALV Thermal Alert Low Value 0000h RO, R/W
40h–43h TL Throttle Levels 00000000h RO, R/W
60h–61h PHL Intel® Xeon® Processor D-1500
Product Family Hot Level
0000h RO, R/W
62h PHLC PHL Control 00h RO, R/W
80h TAS Thermal Alert Status 00h RO, R/W,
R/WC
82h TSPIEN PCI Interrupt Event Enables 00h RO, R/W
84h TSGPEN General Purpose Event Enables 00h RO, R/W
Bit Description
15:9 Reserved
8:0 TS Reading (TSR) — RO. The die temperature with resolution of 1/2 degree C and an offset of -
50C. Thus a reading of 0x121 is 94.5C.
Bit Description
7 Policy Lock-Down Bit — R/W. When written to 1, this bit prevents any more writes to the register
(offset 04h) and to CTT (offset 10h)
6:1 Reserved
0 Catastrophic Power-Down Enable — R/W. When set to 1, the power management logic (PMC)
transitions to the S5 state when a catastrophic temperature is detected by the sensor. The
transition to the S5 state must be unconditional (like the Power Button Override Function). The
thermal sensor and response logic is in the core/main power well; therefore, detection of a
catastrophic temperature is limited to times when this well is powered and out of reset.