Datasheet

Thermal Sensor Registers (D31:F6)
Intel® Xeon® Processor D-1500 Product Family 551
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
16.1.22 PC—Power Management Capabilities Register
Address Offset: 52h–53h Attribute: RO
Default Value: 0023h Size: 16 bits
16.1.23 PCS—Power Management Control And Status Register
Address Offset: 54h–57h Attribute: R/W, RO
Default Value: 0008h Size: 32 bits
16.2 Thermal Memory Mapped Configuration Registers
(Thermal Sensor – D31:F26)
The base memory for these thermal memory mapped configuration registers is
specified in the TBARB (D31:F6:Offset 40h) register. The individual registers are then
accessible at TBARB + Offset.
All registers in Tab l e 16 - 2 are located in the Core Well.
Bit Description
15:11 PME_Support — RO. Indicates PME# is not supported
10 D2_Support — RO. The D2 state is not supported.
9 D1_Support — RO. The D1 state is not supported.
8:6 Aux_Current — RO. PME# from D3COLD state is not supported, therefore this field is 000b.
5 Device Specific Initialization (DSI) — RO. Indicates that device-specific initialization is required.
4 Reserved
3 PME Clock (PMEC) — RO. Does not apply. Hardwired to 0.
2:0 Version (VS) — RO. Indicates support for Revision 1.2 of the PCI Power Management
Specification.
Bit Description
31:24 Data — RO. Does not apply. Hardwired to 0s.
23 Bus Power/Clock Control Enable (BPCCE) — RO. Hardwired to 0.
22 B2/B3 Support (B23) — RO. Does not apply. Hardwired to 0.
21:16 Reserved
15 PME Status (PMES) — RO. This bit is always 0, since this PCI Function does not generate PME#.
14:9 Reserved
8 PME Enable (PMEE) — RO. This bit is always zero, since this PCI Function does not generate
PME#.
7:4 Reserved
3 No Soft Reset — RO. When set 1, this bit indicates that devices transitioning from D3
HOT
to D0
because of PowerState commands do not perform an internal reset. Configuration context is
preserved. Upon transition from D3
HOT
to D0 initialized state, no additional operating system
intervention is required to preserve Configuration Context beyond writing the PowerState bits.
2 Reserved
1:0 Power State (PS) — R/W. This field is used both to determine the current power state of the
Thermal controller and to set a new power state. The values are:
00 = D0 state
11 = D3
HOT
state
If software attempts to write a value of 10b or 01b in to this field, the write operation must
complete normally; however, the data is discarded and no state change occurs.
When in the D3
HOT
states, the Thermal controller’s configuration space is available, but the I/O and
memory spaces are not. Additionally, interrupts are blocked.
When software changes this value from the D3
HOT
state to the D0 state, no internal warm (soft)
reset is generated.