Datasheet
Thermal Sensor Registers (D31:F6)
550 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
16.1.18 INTPN—Interrupt Pin Register
Address Offset: 3Dh Attribute: RO
Default Value: See description Size: 8 bits
16.1.19 TBARB—BIOS Assigned Thermal Base Address Register
Address Offset: 40h–43h Attribute: R/W, RO
Default Value: 00000004h Size: 32 bits
This BAR creates 4 KB of memory space to signify the base address of Thermal memory
mapped configuration registers. This memory space is active when TBARB.SPTYPEN is
asserted. This BAR is owned by the BIOS, and allows the BIOS to locate the Thermal
registers in system memory space. If both TBAR and TBARB are programmed, then the
OS and BIOS each have their own independent “view” of the Thermal registers, and
must use the TSIU register to denote Thermal registers ownership/availability.
16.1.20 TBARBH—BIOS Assigned Thermal Base High
DWord Register
Address Offset: 44h–47h Attribute: R/W
Default Value: 00000000h Size: 32 bits
This BAR extension holds the high 32 bits of the 64 bit TBARB.
16.1.21 PID—PCI Power Management Capability ID Register
Address Offset: 50h–51h Attribute: RO
Default Value: 0001h Size: 16 bits
Bit Description
7:4 Reserved
3:0 Interrupt Pin — RO. This reflects the value of the Device 31 interrupt pin bits 27:24 (TTIP) in
chipset configuration space.
Bit Description
31:12 Thermal Base Address (TBA) — R/W. This field provides the base address for the Thermal logic
memory mapped configuration registers. 4K B bytes are requested by hardwiring bits 11:4 to 0s.
11:4 Reserved
3 Prefetchable (PREF) — RO. Indicates that this BAR is NOT pre-fetchable.
2:1 Address Range (ADDRNG) — RO. Indicates that this BAR can be located anywhere in 64 bit
address space.
0 Space Type Enable (SPTYPEN) — R/W.
0 = Disable.
1 = Enable. When set to 1b by software, enables the decode of this memory BAR.
Bit Description
31:0 Thermal Base Address High (TBAH) — R/W. TBAR bits 61:32.
Bit Description
15:8 Next Capability (NEXT) — RO. Indicates that this is the last capability structure in the list.
7:0 Cap ID (CAP) — RO. Indicates that this pointer is a PCI power management capability