Datasheet

Thermal Sensor Registers (D31:F6)
Intel® Xeon® Processor D-1500 Product Family 547
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
16.1.5 RID—Revision Identification Register
Address Offset: 08h Attribute: RO
Default Value: 00h Size: 8 bits
16.1.6 PI— Programming Interface Register
Address Offset: 09h Attribute: RO
Default Value: 00h Size: 8 bits
16.1.7 SCC—Sub Class Code Register
Address Offset: 0Ah Attribute: RO
Default Value: 80h Size: 8 bits
16.1.8 BCC—Base Class Code Register
Address Offset: 0Bh Attribute: RO
Default Value: 11h Size: 8 bits
16.1.9 CLS—Cache Line Size Register
Address Offset: 0Ch Attribute: RO
Default Value: 00h Size: 8 bits
3 Interrupt Status (IS) — RO. Reflects the state of the INTx# signal at the input of the enable/
disable circuit. This bit is a 1 when the INTx# is asserted. This bit is a 0 after the interrupt is cleared
(independent of the state of the Interrupt Disable bit in the command register).
2:0 Reserved
Bit Description
Bit Description
7:0 Revision ID (RID) — RO. This field indicates the device specific revision identifier.
Bit Description
7:0 Programming Interface (PI) — RO. Intel® Xeon® Processor D-1500 Product Family Thermal
logic has no standard programming interface.
Bit Description
7:0 Sub Class Code (SCC) — RO. Value assigned to Intel® Xeon® Processor D-1500 Product Family
Thermal logic.
Bit Description
7:0 Base Class Code (BCC) — RO. Value assigned to Intel® Xeon® Processor D-1500 Product Family
Thermal logic.
Bit Description
7:0 Cache Line Size (CLS) — RO. Does not apply to PCI Bus Target-only devices.