Datasheet

Thermal Sensor Registers (D31:F6)
546 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
16.1.2 DID—Device Identification Register
Offset Address: 02h–03h Attribute: RO
Default Value: 3A32h Size: 16 bits
16.1.3 CMD—Command Register
Address Offset: 04h–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
16.1.4 STS—Status Register
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 0010h Size: 16 bits
Bit Description
15:0 Device ID (DID) — RO. Indicates the device number assigned by the SIG.
Bit Description
15:11 Reserved
10 Interrupt Disable (ID) — R/W. Enables the device to assert an INTx#.
0 = When cleared, the INTx# signal may be asserted.
1 = When set, the Thermal logic’s INTx# signal will be de-asserted.
9 FBE (Fast Back to Back Enable) — RO. Hardwired to 0.
8 SEN (SERR Enable) — RO. Hardwired to 0.
7 WCC (Wait Cycle Control) — RO. Hardwired to 0.
6 PER (Parity Error Response) — RO. Hardwired to 0.
5 VPS (VGA Palette Snoop) — RO. Hardwired to 0.
4 MWI (Memory Write and Invalidate Enable) — RO. Hardwired to 0.
3 SCE (Special Cycle Enable) — RO. Hardwired to 0.
2 BME (Bus Master Enable) — R/W.
0 = Function disabled as bus master.
1 = Function enabled as bus master.
1 Memory Space Enable (MSE) — R/W.
0 = Disable
1 = Enable. Enables memory space accesses to the Thermal registers.
0 IOS (I/O Space) — RO. The Thermal logic does not implement IO Space; therefore, this bit is
hardwired to 0.
Bit Description
15 Detected Parity Error (DPE) — R/WC. This bit is set whenever a parity error is seen on the
internal interface for this function, regardless of the setting of bit 6 in the command register.
Software clears this bit by writing a 1 to this bit location.
14 SERR# Status (SERRS) — RO. Hardwired to 0.
13 Received Master Abort (RMA) — RO. Hardwired to 0.
12 Received Target Abort (RTA) — RO. Hardwired to 0.
11 Signaled Target-Abort (STA) — RO. Hardwired to 0.
10:9 DEVSEL# Timing Status (DEVT) — RO. Hardwired to 0.
8 Master Data Parity Error (MDPE) — RO. Hardwired to 0.
7 Fast Back to Back Capable (FBC) — RO. Hardwired to 0.
6 Reserved
5 66 MHz Capable (C66) — RO. Hardwired to 0.
4 Capabilities List Exists (CLIST) — RO. Indicates that the controller contains a capabilities pointer
list. The first item is pointed to by looking at configuration offset 34h.