Datasheet

Serial Peripheral Interface (SPI)
544 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: This register is not writable when the SPI Configuration Lock-Down bit (MBARB + 00h:15) is set.
15.4.17 OPMENU—Opcode Menu Configuration Register (GbE LAN
Memory Mapped Configuration Registers)
Memory Address: MBARB + 98h Attribute: R/W
Default Value: 0000000000000000h Size: 64 bits
Eight entries are available in this register to give GbE a sufficient set of commands for
communicating with the flash device, while also restricting what malicious software can
do. This keeps the hardware flexible enough to operate with a wide variety of SPI
devices.
Note: It is recommended that GbE avoid programming Write Enable opcodes in this menu.
Malicious software could then perform writes and erases to the SPI flash without using
the atomic cycle mechanism. This could cause functional failures in a shared flash
environment. Write Enable opcodes should only be programmed in the Prefix Opcodes.
This register is not writable when the SPI Configuration Lock-Down bit (MBARB +
00h:15) is set.
5:4 Opcode Type 2 — R/W. See the description for bits 1:0
3:2 Opcode Type 1 — R/W. See the description for bits 1:0
1:0 Opcode Type 0 — R/W. This field specifies information about the corresponding Opcode 0. This
information allows the hardware to 1) know whether to use the address field and 2) provide BIOS
and Shared Flash protection capabilities. The encoding of the two bits is:
00 = No address associated with this Opcode; Read cycle type
01 = No address associated with this Opcode; Write cycle type
10 = Address required; Read cycle type
11 = Address required; Write cycle type
Bit Description
Bit Description
63:56 Allowable Opcode 7 — R/W. See the description for bits 7:0
55:48 Allowable Opcode 6 — R/W. See the description for bits 7:0
47:40 Allowable Opcode 5 — R/W. See the description for bits 7:0
39:32 Allowable Opcode 4 — R/W. See the description for bits 7:0
31:24 Allowable Opcode 3 — R/W. See the description for bits 7:0
23:16 Allowable Opcode 2 — R/W. See the description for bits 7:0
15:8 Allowable Opcode 1 — R/W. See the description for bits 7:0
7:0 Allowable Opcode 0 — R/W. Software programs an SPI opcode into this field for use when initiating
SPI commands through the Control Register.