Datasheet

Serial Peripheral Interface (SPI)
Intel® Xeon® Processor D-1500 Product Family 543
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.4.15 PREOP—Prefix Opcode Configuration Register (GbE LAN
Memory Mapped Configuration Registers)
Memory Address: MBARB + 94h Attribute: R/W
Default Value: 0000h Size: 16 bits
Note: This register is not writable when the SPI Configuration Lock-Down bit (MBARB + 00h:15) is set.
15.4.16 OPTYPE—Opcode Type Configuration Register (GbE LAN
Memory Mapped Configuration Registers)
Memory Address: MBARB + 96h Attribute: R/W
Default Value: 0000h Size: 16 bits
Entries in this register correspond to the entries in the Opcode Menu Configuration
register.
Note: The definition below only provides write protection for opcodes that have addresses
associated with them. Therefore, any erase or write opcodes that do not use an address
should be avoided (for example, “Chip Erase” and “Auto-Address Increment Byte
Program”).
3 Sequence Prefix Opcode Pointer (SPOP) — R/W. This field selects one of the two programmed
prefix opcodes for use when performing an Atomic Cycle Sequence. A value of 0 points to the opcode
in the least significant byte of the Prefix Opcodes register. By making this programmable, Intel®
Xeon® Processor D-1500 Product Family supports flash devices that have different opcodes for
enabling writes to the data space versus status register.
2 Atomic Cycle Sequence (ACS) — R/W. When set to 1 along with the SCGO assertion, Intel®
Xeon® Processor D-1500 Product Family will execute a sequence of commands on the SPI interface
without allowing the LAN component to arbitrate and interleave cycles. The sequence is composed
of:
• Atomic Sequence Prefix Command (8-bit opcode only)
• Primary Command specified below by software (can include address and data)
• Polling the Flash Status Register (opcode 05h) until bit 0 becomes 0b.
The SPI Cycle in Progress bit remains set and the Cycle Done Status bit remains unset until the Busy
bit in the Flash Status Register returns 0.
1 SPI Cycle Go (SCGO) — R/WS. This bit always returns 0 on reads. However, a write to this register
with a ‘1’ in this bit starts the SPI cycle defined by the other bits of this register. The “SPI Cycle in
Progress” (SCIP) bit gets set by this action. Hardware must ignore writes to this bit while the Cycle
In Progress bit is set.
Hardware allows other bits in this register to be programmed for the same transaction when writing
this bit to 1. This saves an additional memory write.
0 Reserved
Bit Description
Bit Description
15:8 Prefix Opcode 1— R/W. Software programs an SPI opcode into this field that is permitted to run as
the first command in an atomic cycle sequence.
7:0 Prefix Opcode 0 — R/W. Software programs an SPI opcode into this field that is permitted to run as
the first command in an atomic cycle sequence.
Bit Description
15:14 Opcode Type 7 — R/W. See the description for bits 1:0
13:12 Opcode Type 6 — R/W. See the description for bits 1:0
11:10 Opcode Type 5 — R/W. See the description for bits 1:0
9:8 Opcode Type 4 — R/W. See the description for bits 1:0
7:6 Opcode Type 3 — R/W. See the description for bits 1:0