Datasheet

Serial Peripheral Interface (SPI)
542 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.4.13 SSFS—Software Sequencing Flash Status Register (GbE
LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 90h Attribute: RO, R/WC
Default Value: 00h Size: 8 bits
Note: The Software Sequencing control and status registers are reserved if the hardware
sequencing control and status registers are used.
15.4.14 SSFC—Software Sequencing Flash Control Register (GbE
LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 91h Attribute: R/W
Default Value: 000000h Size: 24 bits
Bit Description
7:5 Reserved
4 Access Error Log (AEL) — RO. This bit reflects the value of the Hardware Sequencing Status AEL
register.
3 Flash Cycle Error (FCERR) — R/WC. Hardware sets this bit to 1 when a programmed access is
blocked from running on the SPI interface due to one of the protection policies or when any of the
programmed cycle registers is written while a programmed access is already in progress. This bit
remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host
partition reset in an Intel ME enabled system.
2 Cycle Done Status — R/WC. Intel® Xeon® Processor D-1500 Product Family sets this bit to 1 when
the SPI Cycle completes (that is, SCIP bit is 0) after software sets the GO bit. This bit remains
asserted until cleared by software writing a 1 or hardware reset due to a global reset or host
partition reset in an Intel ME enabled system. When this bit is set and the SPI SMI# Enable bit is set,
an internal signal is asserted to the SMI# generation block. Software must make sure this bit is
cleared prior to enabling the SPI SMI# assertion for a new programmed access.
1Reserved
0 SPI Cycle In Progress (SCIP) — RO. Hardware sets this bit when software sets the SPI Cycle Go
bit in the Command register. This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can determine when read data is
valid and/or when it is safe to begin programming the next command. Software must only program
the next command when this bit is 0.
Bit Description
23:19 Reserved
18:16 SPI Cycle Frequency (SCF) — R/W. This register sets frequency to use for all SPI software
sequencing cycles (write, erase, fast read, read status, and so on) except for the read cycle which
always run at 20 MHz.
000 = 20 MHz
001 = 33 MHz
All other values = Reserved.
This register is locked when the SPI Configuration Lock-Down bit is set.
15 Reserved
14 Data Cycle (DS) — R/W. When set to 1, there is data that corresponds to this transaction. When 0,
no data is delivered for this cycle, and the dBC and data fields themselves are don’t cares.
13:8 Data Byte Count (dBC) — R/W. This field specifies the number of bytes to shift in or out during the
data portion of the SPI cycle. The valid settings (in decimal) are any value from 0 to 3. The number
of bytes transferred is the value of this field plus 1.
When this field is 00b, then there is 1 byte to transfer and that 11b means there are 4 bytes to
transfer.
7Reserved
6:4 Cycle Opcode Pointer (COP) — R/W. This field selects one of the programmed opcodes in the
Opcode Menu to be used as the SPI Command/Opcode. In the case of an Atomic Cycle Sequence,
this determines the second command.