Datasheet

Serial Peripheral Interface (SPI)
540 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register (GbE
LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 54h Attribute: RO
Default Value: 00000000h Size: 32 bits
15.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register (GbE
LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 58h Attribute: RO
Default Value: 00000000h Size: 32 bits
15.4.9 FREG2—Flash Region 2 (Intel
®
ME) Register (GbE LAN
Memory Mapped Configuration Registers)
Memory Address: MBARB + 5Ch Attribute: RO
Default Value: 00000000h Size: 32 bits
15.4.10 FREG3—Flash Region 3 (GbE) Register (GbE LAN Memory
Mapped Configuration Registers)
Memory Address: MBARB + 60h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:29 Reserved
28:16 Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 0 Limit.
The value in this register is loaded from the contents in the Flash Descriptor.FLREG0.Region Limit.
15:13 Reserved
12:0 Region Base (RB) — RO. This specifies address bits 24:12 for the Region 0 Base
The value in this register is loaded from the contents in the Flash Descriptor.FLREG0.Region Base.
Bit Description
31:29 Reserved
28:16 Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 1 Limit.
The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Limit.
15:13 Reserved
12:0 Region Base (RB) — RO. This specifies address bits 24:12 for the Region 1 Base
The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Base.
Bit Description
31:29 Reserved
28:16 Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 2 Limit.
The value in this register is loaded from the contents in the Flash Descriptor.FLREG2.Region Limit.
15:13 Reserved
12:0 Region Base (RB) — RO. This specifies address bits 24:12 for the Region 2 Base
The value in this register is loaded from the contents in the Flash Descriptor.FLREG2.Region Base.
Bit Description
31:29 Reserved
28:16 Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 3 Limit.
The value in this register is loaded from the contents in the Flash Descriptor.FLREG3.Region Limit.
15:13 Reserved