Datasheet

Functional Description
54 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
• Generates the message on the downstream port
• When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/
F2/F3/F4/F5/F6/F7:Offset 58h:Bit 4) to indicate the command has completed. If
SLCTL.CCE and SLCTL.HPE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bit 5) are
set, the root port generates an interrupt.
The command completed register (SLSTS.CC) applies only to commands issued by
software to control the Attention Indicator (SLCTL.AIC), Power Indicator (SLCTL.PIC),
or Power Controller (SLCTL.PCC). However, writes to other parts of the Slot Control
Register would invariably end up writing to the indicators and power controller fields.
Hence, any write to the Slot Control Register is considered a command and if enabled,
will result in a command complete interrupt. The only exception to this rule is a write to
disable the command complete interrupt which will not result in a command
complete interrupt.
A single write to the Slot Control register is considered to be a single command, and,
hence, receives a single command complete, even if the write affects more than one
field in the Slot Control Register.
3.2.5.3 Attention Button Detection
When an attached device is ejected, an attention button could be pressed by the user.
This attention button press will result in a the PCI Express* message
“Attention_Button_Pressed” from the device. Upon receiving this message, the root
port will set SLSTS.ABP (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 5Ah:Bit 0).
If SLCTL.ABE (D28:F0/F1/F2/F3/F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/
F2/F3/F4/F5/F6/F7:Offset 58h:Bit 5) are set, the Hot-Plug controller will also generate
an interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is
already set, a new interrupt will not be generated.
3.2.5.4 SMI/SCI Generation
Interrupts for Hot-Plug events are not supported on legacy operating systems. To
support Hot-Plug on n on-PCI Express aware operating systems, Hot-Plug events can
be routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3/F4/F5/F6/
F7:Offset D8h:Bit 30) must be set. When set, enabled Hot-Plug events will cause
SMSCS.HPCS (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:Bit 30) to be set.
Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME
(D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset D8h:Bit 1). When this bit is set, Hot-Plug events
can cause SMI status bits in SMSCS to be set. Supported Hot-Plug events and their
corresponding SMSCS bit are:
• Command Completed – SCSCS.HPCCM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset
DCh:Bit 3)
• Presence Detect Changed – SMSCS.HPPDM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset
DCh:Bit 1)
• Attention Button Pressed – SMSCS.HPABM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset
DCh:Bit 2)
• Link Active State Changed – SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset
DCh:Bit 4)