Datasheet

Serial Peripheral Interface (SPI)
538 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.4.3 HSFC—Hardware Sequencing Flash Control Register (GbE
LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 06h Attribute: R/W, R/WS
Default Value: 0000h Size: 16 bits
15.4.4 FADDR—Flash Address Register (GbE LAN Memory Mapped
Configuration Registers)
Memory Address: MBARB + 08h Attribute: R/W
Default Value: 00000000h Size: 32 bits
1 Flash Cycle Error (FCERR) — R/W/C. Hardware sets this bit to 1 when an program register access
is blocked to the FLASH due to one of the protection policies or when any of the programmed cycle
registers is written while a programmed access is already in progress. This bit remains asserted until
cleared by software writing a 1 or until hardware reset occurs due to a global reset or host partition
reset in an Intel ME enabled system. Software must clear this bit before setting the FLASH Cycle GO
bit in this register.
0 Flash Cycle Done (FDONE) — R/W/C. Intel® Xeon® Processor D-1500 Product Family sets this bit
to 1 when the SPI Cycle completes after software previously set the FGO bit. This bit remains
asserted until cleared by software writing a 1 or hardware reset due to a global reset or host
partition reset in an Intel ME enabled system. When this bit is set and the SPI SMI# Enable bit is set,
an internal signal is asserted to the SMI# generation block. Software must make sure this bit is
cleared prior to enabling the SPI SMI# assertion for a new programmed access.
Bit Description
Bit Description
15:10 Reserved
9:8 Flash Data Byte Count (FdBC) — R/W. This field specifies the number of bytes to shift in or out
during the data portion of the SPI cycle. The contents of this register are 0s based with 0b
representing 1 byte and 11b representing 4 bytes. The number of bytes transferred is the value of
this field plus 1.
This field is ignored for the Block Erase command.
7:3 Reserved
2:1 FLASH Cycle (FCYCLE) — R/W. This field defines the Flash SPI cycle type generated to the FLASH
when the FGO bit is set as defined below:
00 = Read (1 up to 4 bytes by setting FdBC)
01 = Reserved
10 = Write (1 up to 4 bytes by setting FdBC)
11 = Block Erase
0 Flash Cycle Go (FGO) — R/W/S. A write to this register with a 1 in this bit initiates a request to the
Flash SPI Arbiter to start a cycle. This register is cleared by hardware when the cycle is granted by
the SPI arbiter to run the cycle on the SPI bus. When the cycle is complete, the FDONE bit is set.
Software is forbidden to write to any register in the HSFLCTL register between the FGO bit getting
set and the FDONE bit being cleared. Any attempt to violate this rule will be ignored by hardware.
Hardware allows other bits in this register to be programmed for the same transaction when writing
this bit to 1. This saves an additional memory write.
This bit always returns 0 on reads.
Bit Description
31:25 Reserved
24:0 Flash Linear Address (FLA) — R/W. The FLA is the starting byte linear address of a SPI Read or
Write cycle or an address within a Block for the Block Erase command. The Flash Linear Address
must fall within a region for which BIOS has access permissions.