Datasheet

Serial Peripheral Interface (SPI)
536 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
computer leaves the manufacturing floor. Intel® Xeon® Processor D-1500 Product
Family Flash controller does not read this information. FFh is suggested to reduce
programming time.
15.4 GbE SPI Flash Program Registers
The GbE Flash registers are memory-mapped with a base address MBARB found in the
GbE LAN register chapter Device 25: Function 0: Offset 14h. The individual registers
are then accessible at MBARB + Offset as indicated in the following table.
These memory mapped registers must be accessed in byte, word, or DWord quantities.
Note: These register are only applicable when SPI flash is used in descriptor mode.
Table 15-2. Gigabit LAN SPI Flash Program Register Address Map (GbE LAN Memory
Mapped Configuration Registers)
MBARB +
Offset
Mnemonic Register Name Default Attribute
00h–03h GLFPR Gigabit LAN Flash Primary Region 00000000h RO
04h–05h HSFS Hardware Sequencing Flash Status 0000h RO, R/WC, R/
W
06h–07h HSFC Hardware Sequencing Flash Control 0000h R/W, R/WS
08h–0Bh FADDR Flash Address 00000000h R/W
0Ch–0Fh — Reserved 00000000h
10h–13h FDATA0 Flash Data 0 00000000h R/W
14h–4Fh — Reserved 00000000h
50h–53h FRAP Flash Region Access Permissions 00000000h RO, R/W
54h–57h FREG0 Flash Region 0 00000000h RO
58h–5Bh FREG1 Flash Region 1 00000000h RO
5Ch–5F FREG2 Flash Region 2 00000000h RO
60h–63h FREG3 Flash Region 3 00000000h RO
64h–73h — Reserved for Future Flash Regions
74h–77h PR0 Flash Protected Range 0 00000000h R/W
78h–7Bh PR1 Flash Protected Range 1 00000000h R/W
7Ch–8Fh — Reserved
90h SSFS Software Sequencing Flash Status 00h RO, R/WC
91h–93h SSFC Software Sequencing Flash Control 000000h R/W
94h–95h PREOP Prefix Opcode Configuration 0000h R/W
96h–97h OPTYPE Opcode Type Configuration 0000h R/W
98h–9Fh OPMENU Opcode Menu Configuration 000000000000
0000h
R/W
A0h–DFh — Reserved