Datasheet

Serial Peripheral Interface (SPI)
Intel® Xeon® Processor D-1500 Product Family 535
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.1.30 SRDL—Soft Reset Data Lock Register (SPI Memory Mapped
Configuration Registers)
Memory Address: SPIBAR + F0h Attribute: R/WL
Default Value: 00000000h Size: 32 bits
15.1.31 SRDC—Soft Reset Data Control Register (SPI Memory
Mapped Configuration Registers)
Memory Address: SPIBAR + F4h Attribute: R/WL
Default Value: 00000000h Size: 32 bits
15.1.32 SRD—Soft Reset Data Register (SPI Memory Mapped
Configuration Registers)
Memory Address: SPIBAR + F8h Attribute: R/WL
Default Value: 00000000h Size: 32 bits
15.2 Flash Descriptor Records
The following sections describe the data structure of the Flash Descriptor on the SPI
device. These are not registers within Intel® Xeon® Processor D-1500 Product Family.
15.3 OEM Section
Memory Address: F00h
Default Value: Size: 256 Bytes
256 Bytes are reserved at the top of the Flash Descriptor for use by the OEM. The
information stored by the OEM can only be written during the manufacturing process as
the Flash Descriptor read/write permissions must be set to Read Only when the
Bit Description
31:1 Reserved
0 Set_Stap Lock (SSL) — R/WL.
0 = The SRDL (this register), SRDC (SPIBAR+F4h), and SRD (SPIBAR+F4h) registers are writeable.
1 = The SRDL (this register), SRDC (SPIBAR+F4h), and SRD (SPIBAR+F4h) registers are locked.
Note: That this bit is reset to ‘0’ on CF9h resets.
Bit Description
31:1 Reserved
0 Soft Reset Data Select (SRDS) — R/WL.
0 = The Set_Strap data sends the default processor configuration data.
1 = The Set_Strap message bits come from the Set_Strap Msg Data register.
Notes:
1. This bit is reset by the RSMRST# or when the Resume well loses power.
2. This bit is locked by the SSL bit (SPIBAR+F0h:bit 0).
Bit Description
31:14 Reserved
13:0 Set_Stap Data (SSD) — R/WL.
Notes:
1. These bits are reset by the RSMRST#, or when the Resume well loses power.
2. These bits are locked by the SSL bit (SPIBAR+F0h:bit 0).