Datasheet

Serial Peripheral Interface (SPI)
534 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.1.29 FPB—Flash Partition Boundary Register (SPI Memory
Mapped Configuration Registers)
Memory Address: SPIBAR + D0h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
4 Write Enable on Write Status (UWEWS) — R/W. This register is locked by the Vendor Component
Lock (UVCL) bit.
0 = No automatic write of 00h will be made to the SPI flash’s status register)
1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and erase to the SPI
flash. 06h 01h 00h is the opcode sequence used to unlock the Status register.
Notes:
1. This bit should not be set to 1 if there are non volatile bits in the SPI flash’s status register. This
may lead to premature flash wear out.
2. This is not an atomic sequence. If the SPI component’s status register is non-volatile, then
BIOS should issue an atomic software sequence cycle to unlock the flash part.
3. Bit 3 and bit 4 should NOT be both set to 1.
3 Upper Write Status Required (UWSR) — R/W. This register is locked by the Vendor Component
Lock (UVCL) bit.
0 = No automatic write of 00h will be made to the SPI flash’s status register)
1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and erase to the SPI
flash. 50h 01h 00h is the opcode sequence used to unlock the Status register.
Notes:
1. This bit should not be set to ‘1’ if there are non volatile bits in the SPI flash’s status register. This
may lead to premature flash wear out.
2. This is not an atomic sequence. If the SPI component’s status register is non-volatile, then
BIOS should issue an atomic software sequence cycle to unlock the flash part.
3. Bit 3 and bit 4 should NOT be both set to 1.
2 Upper Write Granularity (UWG) — R/W. This register is locked by the Vendor Component Lock
(UVCL) bit.
0 = 1 Byte
1 = 64 Byte
Notes:
1. If more than one Flash component exists, this field must be set to the lowest common write
granularity of the different Flash components.
2. If using 64 B write, BIOS must ensure that multiple byte writes do not occur over 256 B
boundaries. This will lead to corruption as the write will wrap around the page boundary on the
SPI flash part. This is a a feature page writable SPI flash.
1:0 Upper Block/Sector Erase Size (UBES)— R/W. This field identifies the erasable sector size for all
Flash components.
Valid Bit Settings:
00 = 256 Byte
01 = 4 KB
10 = 8 KB
11 = 64 KB
This register is locked by the Vendor Component Lock (UVCL) bit.
Hardware takes no action based on the value of this register. The contents of this register are to be
used only by software and can be read in the HSFSTS.BERASE register in both the BIOS and the GbE
program registers if FLA is greater or equal to FPBA.
Bit Description
Bit Description
31:13 Reserved
12:0 Flash Partition Boundary Address (FPBA) — RO. This register reflects the value of Flash
Descriptor Component FPBA field.