Datasheet

Serial Peripheral Interface (SPI)
Intel® Xeon® Processor D-1500 Product Family 533
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.1.28 UVSCC— Host Upper Vendor Specific Component
Capabilities Register (SPI Memory Mapped Configuration
Registers)
Memory Address: SPIBAR + C8h Attribute: RO, R/WL
Default Value: 00000000h Size: 32 bits
Note: All attributes described in UVSCC must apply to all flash space equal to or above the
FPBA, even if it spans between two separate flash parts. This register is only applicable
when SPI device is in descriptor mode.
Note: To prevent this register from being modified you must use LVSCC.VCL bit.
4 Write Enable on Write Status (LWEWS) — R/W. This register is locked by the Vendor Component
Lock (LVCL) bit.
0 = No automatic write of 00h will be made to the SPI flash’s status register)
1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and erase to the SPI
flash. 06h 01h 00h is the opcode sequence used to unlock the Status register.
Notes:
1. This bit should not be set to 1 if there are non-volatile bits in the SPI flash’s status register. This
may lead to premature flash wear out.
2. This is not an atomic sequence. If the SPI component’s status register is non-volatile, then BIOS
should issue an atomic software sequence cycle to unlock the flash part.
3. Bit 3 and bit 4 should NOT be both set to 1.
3 Lower Write Status Required (LWSR) — R/W. This register is locked by the Vendor Component
Lock (LVCL) bit.
0 = No automatic write of 00h will be made to the SPI flash’s status register)
1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and erase to the SPI
flash. 50h 01h 00h is the opcode sequence used to unlock the Status register.
Notes:
1. This bit should not be set to 1 if there are non volatile bits in the SPI flash’s status register. This
may lead to premature flash wear out.
2. This is not an atomic sequence. If the SPI component’s status register is non-volatile, then BIOS
should issue an atomic software sequence cycle to unlock the flash part.
3. Bit 3 and bit 4 should NOT be both set to 1.
2 Lower Write Granularity (LWG) — R/W. This register is locked by the Vendor Component Lock
(LVCL) bit.
0 = 1 Byte
1 = 64 Byte
Notes:
1. If more than one Flash component exists, this field must be set to the lowest common write
granularity of the different Flash components.
2. If using 64 B write, BIOS must ensure that multiple byte writes do not occur over 256 B
boundaries. This will lead to corruption as the write will wrap around the page boundary on the
SPI flash part. This is a a feature page writable SPI flash.
1:0 Lower Block/Sector Erase Size (LBES)— R/W. This field identifies the erasable sector size for all
Flash components.
00 = 256 Byte
01 = 4 KB
10 = 8 KB
11 = 64 KB
This register is locked by the Vendor Component Lock (LVCL) bit.
Hardware takes no action based on the value of this register. The contents of this register are to be
used only by software and can be read in the HSFSTS.BERASE register in both the BIOS and the GbE
program registers if FLA is less than FPBA.
Bit Description
Bit Description
31:16 Reserved
15:8 Upper Erase Opcode (UEO)— R/W. This register is programmed with the Flash erase instruction
opcode required by the vendor’s Flash component.
This register is locked by the Vendor Component Lock (UVCL) bit.
7:5 Reserved