Datasheet

Serial Peripheral Interface (SPI)
Intel® Xeon® Processor D-1500 Product Family 531
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR +
00h:15) is set.
15.1.23 BBAR—BIOS Base Address Configuration Register (SPI
Memory Mapped Configuration Registers)
Memory Address: SPIBAR + A0h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Eight entries are available in this register to give BIOS a sufficient set of commands for
communicating with the flash device, while also restricting what malicious software can
do. This keeps the hardware flexible enough to operate with a wide variety of SPI
devices.
15.1.24 FDOC—Flash Descriptor Observability Control Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + B0h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register that can be used to observe the contents of the Flash Descriptor that is
stored in Intel® Xeon® Processor D-1500 Product Family Flash Controller. This register
is only applicable when SPI device is in descriptor mode.
15:8 Allowable Opcode 1 — R/W. See the description for bits 7:0
7:0 Allowable Opcode 0 — R/W. Software programs an SPI opcode into this field for use when initiating
SPI commands through the Control Register.
Bit Description
Bit Description
31:24 Reserved
23:8 Bottom of System Flash— R/W. This field determines the bottom of the System BIOS. Intel®
Xeon® Processor D-1500 Product Family will not run programmed commands nor memory reads
whose address field is less than this value. this field corresponds to bits 23:8 of the 3-byte address;
bits 7:0 are assumed to be 00h for this vector when comparing to a potential SPI address.
Note: The SPI host controller prevents any programmed cycle using the address register with an
address less than the value in this register. Some flash devices specify that the Read ID
command must have an address of 0000h or 0001h. If this command must be supported
with these devices, it must be performed with the BIOS BAR.
7:0 Reserved
Bit Description
31:15 Reserved
14:12 Flash Descriptor Section Select (FDSS) — R/W. Selects which section within the loaded Flash
Descriptor to observe.
000 = Flash Signature and Descriptor Map
001 = Component
010 = Region
011 = Master
111 = Reserved
11:2 Flash Descriptor Section Index (FDSI) — R/W. Selects the DW offset within the Flash Descriptor
Section to observe.
1:0 Reserved