Datasheet

Serial Peripheral Interface (SPI)
Intel® Xeon® Processor D-1500 Product Family 529
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.1.20 PREOP—Prefix Opcode Configuration Register (SPI
Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 94h Attribute: R/W
Default Value: 0000h Size: 16 bits
Note: This register is not writable when the Flash Configuration Lock-Down bit (SPIBAR + 04h:15) is set.
18:16 SPI Cycle Frequency (SCF) — R/W. This register sets frequency to use for all SPI software
sequencing cycles (write, erase, fast read, read status, and so on) except for the read cycle
which always run at 20 MHz.
000 = 20 MHz
001 = 33 MHz
100 = 50 MHz
All other values reserved.
This register is locked when the SPI Configuration Lock-Down bit is set.
15 SPI SMI# Enable (SME) — R/W. When set to 1, the SPI asserts an SMI# request whenever
the Cycle Done Status bit is 1.
14 Data Cycle (DS) — R/W. When set to 1, there is data that corresponds to this transaction.
When 0, no data is delivered for this cycle, and the dBC and data fields themselves are don’t
cares.
13:8 Data Byte Count (dBC) — R/W. This field specifies the number of bytes to shift in or out during
the data portion of the SPI cycle. The valid settings (in decimal) are any value from 0 to 63. The
number of bytes transferred is the value of this field plus 1.
When this field is 00_0000b, there is 1 byte to transfer and that 11_1111b means there are 64
bytes to transfer.
7 Reserved
6:4 Cycle Opcode Pointer (COP) — R/W. This field selects one of the programmed opcodes in the
Opcode Menu to be used as the SPI Command/Opcode. In the case of an Atomic Cycle
Sequence, this determines the second command.
3 Sequence Prefix Opcode Pointer (SPOP) — R/W. This field selects one of the two
programmed prefix opcodes for use when performing an Atomic Cycle Sequence. A value of 0
points to the opcode in the least significant byte of the Prefix Opcodes register. By making this
programmable, Intel® Xeon® Processor D-1500 Product Family supports flash devices that have
different opcodes for enabling writes to the data space versus status register.
2 Atomic Cycle Sequence (ACS) — R/W. When set to 1 along with the SCGO assertion, Intel®
Xeon® Processor D-1500 Product Family will execute a sequence of commands on the SPI
interface without allowing the LAN component to arbitrate and interleave cycles. The sequence is
composed of:
• Atomic Sequence Prefix Command (8-bit opcode only)
• Primary Command specified below by software (can include address and data)
• Polling the Flash Status Register (opcode 05h) until bit 0 becomes 0b.
The SPI Cycle in Progress bit remains set and the Cycle Done Status bit remains unset until the
Busy bit in the Flash Status Register returns 0.
1 SPI Cycle Go (SCGO) — R/WS. This bit always returns 0 on reads. However, a write to this
register with a 1 in this bit starts the SPI cycle defined by the other bits of this register. The “SPI
Cycle in Progress” (SCIP) bit gets set by this action. Hardware must ignore writes to this bit
while the Cycle In Progress bit is set.
Hardware allows other bits in this register to be programmed for the same transaction when
writing this bit to 1. This saves an additional memory write.
0 Reserved
Bit Description
Bit Description
15:8 Prefix Opcode 1— R/W. Software programs an SPI opcode into this field that is permitted to run as
the first command in an atomic cycle sequence.
7:0 Prefix Opcode 0 — R/W. Software programs an SPI opcode into this field that is permitted to run as
the first command in an atomic cycle sequence.