Datasheet

Serial Peripheral Interface (SPI)
528 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.1.18 SSFS—Software Sequencing Flash Status Register (SPI
Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 90h Attribute: RO, R/WC
Default Value: 00h Size: 8 bits
Note: The Software Sequencing control and status registers are reserved if the hardware
sequencing control and status registers are used.
15.1.19 SSFC—Software Sequencing Flash Control Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 91h Attribute: R/W
Default Value: F80000h Size: 24 bits
28:16 Protected Range Limit — R/W. This field corresponds to FLA address bits 24:12 and specifies the
upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit
comparison. Any address greater than the value programmed in this field is unaffected by this
protected range.
15 Read Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this
register are valid and that read directed to addresses between them (inclusive) must be blocked by
hardware. The base and limit fields are ignored when this bit is cleared.
14:13 Reserved
12:0 Protected Range Base — R/W. This field corresponds to FLA address bits 24:12 and specifies the
lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base
comparison. Any address less than the value programmed in this field is unaffected by this protected
range.
Bit Description
Bit Description
7:5 Reserved
4 Access Error Log (AEL) — RO. This bit reflects the value of the Hardware Sequencing Status AEL
register.
3 Flash Cycle Error (FCERR) — R/WC. Hardware sets this bit to 1 when a programmed access is
blocked from running on the SPI interface due to one of the protection policies or when any of the
programmed cycle registers is written while a programmed access is already in progress. This bit
remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host
partition reset in an Intel ME enabled system.
2 Cycle Done Status — R/WC. Intel® Xeon® Processor D-1500 Product Family sets this bit to 1 when
the SPI Cycle completes
(that is, SCIP bit is 0) after software sets the GO bit. This bit remains asserted until cleared by
software writing a 1 or hardware reset due to a global reset or host partition reset in an Intel ME
enabled system. When this bit is set and the SPI SMI# Enable bit is set, an internal signal is asserted
to the SMI# generation block. Software must make sure this bit is cleared prior to enabling the SPI
SMI# assertion for a new programmed access.
1Reserved
0 SPI Cycle In Progress (SCIP) — RO. Hardware sets this bit when software sets the SPI Cycle Go
bit in the Command register. This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can determine when read data is
valid and/or when it is safe to begin programming the next command. Software must only program
the next command when this bit is 0.
Bit Description
23:19 Reserved – BIOS must set this field to ‘11111’b