Datasheet

Serial Peripheral Interface (SPI)
Intel® Xeon® Processor D-1500 Product Family 527
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.1.16 PR3—Protected Range 3 Register (SPI Memory Mapped
Configuration Registers)
Memory Address: SPIBAR + 80h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register can not be written when the FLOCKDN bit is set to 1.
15.1.17 PR4—Protected Range 4 Register (SPI Memory Mapped
Configuration Registers)
Memory Address: SPIBAR + 84h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register can not be written when the FLOCKDN bit is set to 1.
Bit Description
31 Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this
register are valid and that writes and erases directed to addresses between them (inclusive) must be
blocked by hardware. The base and limit fields are ignored when this bit is cleared.
30:29 Reserved
28:16 Protected Range Limit — R/W. This field corresponds to FLA address bits 24:12 and specifies the
upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit
comparison. Any address greater than the value programmed in this field is unaffected by this
protected range.
15 Read Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this
register are valid and that read directed to addresses between them (inclusive) must be blocked by
hardware. The base and limit fields are ignored when this bit is cleared.
14:13 Reserved
12:0 Protected Range Base — R/W. This field corresponds to FLA address bits 24:12 and specifies the
lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base
comparison. Any address less than the value programmed in this field is unaffected by this protected
range.
Bit Description
31 Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this
register are valid and that writes and erases directed to addresses between them (inclusive) must be
blocked by hardware. The base and limit fields are ignored when this bit is cleared.
30:29 Reserved
28:16 Protected Range Limit — R/W. This field corresponds to FLA address bits 24:12 and specifies the
upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit
comparison. Any address greater than the value programmed in this field is unaffected by this
protected range.
15 Read Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this
register are valid and that read directed to addresses between them (inclusive) must be blocked by
hardware. The base and limit fields are ignored when this bit is cleared.
14:13 Reserved
12:0 Protected Range Base — R/W. This field corresponds to FLA address bits 24:12 and specifies the
lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base
comparison. Any address less than the value programmed in this field is unaffected by this protected
range.
Bit Description
31 Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this
register are valid and that writes and erases directed to addresses between them (inclusive) must be
blocked by hardware. The base and limit fields are ignored when this bit is cleared.
30:29 Reserved