Datasheet

Serial Peripheral Interface (SPI)
524 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 54h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
15.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register (SPI
Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 58h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
23:16 BIOS Master Read Access Grant (BMRAG) — R/W. Each bit [28:16] corresponds to Master[7:0].
BIOS can grant one or more masters read access to the BIOS region 1 overriding the read
permissions in the Flash Descriptor.
Master[1] is Host processor/BIOS, Master[2] is Intel Management Engine, Master[3] is Host
processor/GbE. Master[0] and Master[7:4] are reserved.
The contents of this register are locked by the FLOCKDN bit
15:8 BIOS Region Write Access (BRWA) — RO. Each bit [15:8] corresponds to Regions [7:0]. If the
bit is set, this master can erase and write that particular region through register accesses.
The contents of this register are that of the Flash Descriptor. Flash Master 1 Master Region Write
Access OR a particular master has granted BIOS write permissions in their Master Write Access Grant
register or the Flash Descriptor Security Override strap is set.
7:0 BIOS Region Read Access (BRRA) — RO. Each bit [7:0] corresponds to Regions [7:0]. If the bit is
set, this master can read that particular region through register accesses.
The contents of this register are that of the Flash Descriptor.Flash Master 1.Master Region Write
Access OR a particular master has granted BIOS read permissions in their Master Read Access Grant
register or the Flash Descriptor Security Override strap is set.
Bit Description
Bit Description
31:29 Reserved
28:16 Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 0 Limit.
The value in this register is loaded from the contents in the Flash Descriptor.FLREG0.Region Limit.
15:13 Reserved
12:0 Region Base (RB) / Flash Descriptor Base Address Region (FdBAR) — RO. This specifies
address bits 24:12 for the Region 0 Base
The value in this register is loaded from the contents in the Flash Descriptor.FLREG0.Region Base.
Bit Description
31:29 Reserved
28:16 Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 1 Limit.
The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Limit.
15:13 Reserved
12:0 Region Base (RB) — RO. This specifies address bits 24:12 for the Region 1 Base
The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Base.