Datasheet
Serial Peripheral Interface (SPI)
Intel® Xeon® Processor D-1500 Product Family 523
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.1.5 FDATA0—Flash Data 0 Register (SPI Memory Mapped
Configuration Registers)
Memory Address: SPIBAR + 10h Attribute: R/W
Default Value: 00000000h Size: 32 bits
15.1.6 FDATAN—Flash Data [N] Register (SPI Memory Mapped
Configuration Registers)
Memory Address: SPIBAR + 14h Attribute: R/W
SPIBAR + 18h
SPIBAR + 1Ch
SPIBAR + 20h
SPIBAR + 24h
SPIBAR + 28h
SPIBAR + 2Ch
SPIBAR + 30h
SPIBAR + 34h
SPIBAR + 38h
SPIBAR + 3Ch
SPIBAR + 40h
SPIBAR + 44h
SPIBAR + 48h
SPIBAR + 4Ch
Default Value: 00000000h Size: 32 bits
15.1.7 FRAP—Flash Regions Access Permissions Register (SPI
Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 50h Attribute: RO, R/W
Default Value: 00000202h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
Bit Description
31:0 Flash Data 0 (FD0) — R/W. This field is shifted out as the SPI Data on the Master-Out Slave-In
Data pin during the data portion of the SPI cycle.
This register also shifts in the data from the Master-In Slave-Out pin into this register during the
data portion of the SPI cycle.
The data is always shifted starting with the least significant byte, msb to lsb, followed by the next
least significant byte, msb to lsb, and so on. Specifically, the shift order on SPI in terms of bits within
this register is: 7-6-5-4-3-2-1-0-15-14-13-…8-23-22-…16-31…24 Bit 24 is the last bit shifted out/in.
There are no alignment assumptions; byte 0 always represents the value specified by the cycle
address.
The data in this register may be modified by the hardware during any programmed SPI transaction.
Direct Memory Reads do not modify the contents of this register.
Bit Description
31:0 Flash Data N (FD[N]) — R/W. Similar definition as Flash Data 0. However, this register does not
begin shifting until FD[N-1] has completely shifted in/out.
Bit Description
31:24 BIOS Master Write Access Grant (BMWAG) — R/W. Each bit [31:29] corresponds to
Master[7:0]. BIOS can grant one or more masters write access to the BIOS region 1 overriding the
permissions in the Flash Descriptor.
Master[1] is Host processor/BIOS, Master[2] is Intel Management Engine, Master[3] is Host
processor/GbE. Master[0] and Master[7:4] are reserved.
The contents of this register are locked by the FLOCKDN bit.