Datasheet

Serial Peripheral Interface (SPI)
Intel® Xeon® Processor D-1500 Product Family 521
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.1.2 HSFS—Hardware Sequencing Flash Status Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 04h Attribute: RO, R/WC, R/W
Default Value: 0000h Size: 16 bits
Bit Description
15 Flash Configuration Lock-Down (FLOCKDN) — R/W/L. When set to 1, those Flash Program
Registers that are locked down by this FLOCKDN bit cannot be written. Once set to 1, this bit can
only be cleared by a hardware reset due to a global reset or host partition reset in an Intel ME
enabled system.
14 Flash Descriptor Valid (FDV) — RO. This bit is set to a 1 if the Flash Controller read the correct
Flash Descriptor Signature.
If the Flash Descriptor Valid bit is not 1, software cannot use the Hardware Sequencing registers, but
must use the software sequencing registers. Any attempt to use the Hardware Sequencing registers
will result in the FCERR bit being set.
13 Flash Descriptor Override Pin Strap Status (FDOPSS) — RO. This bit indicates the condition of
the Flash Descriptor Security Override / Intel ME Debug Mode pin strap.
0 = The Flash Descriptor Security Override / Intel ME Debug Mode strap is set using external pull-up
on MFG_MODE_STRAP
1 = No override
12:6 Reserved
5 SPI Cycle In Progress (SCIP)— RO. Hardware sets this bit when software sets the Flash Cycle Go
(FGO) bit in the Hardware Sequencing Flash Control register. This bit remains set until the cycle
completes on the SPI interface. Hardware automatically sets and clears this bit so that software can
determine when read data is valid and/or when it is safe to begin programming the next command.
Software must only program the next command when this bit is 0.
Note: This field is only applicable when in Descriptor mode and Hardware sequencing is being
used.
4:3 Block/Sector Erase Size (BERASE) — RO. This field identifies the erasable sector size for all Flash
components.
Valid Bit Settings:
00 = 256 Byte
01 = 4 K Byte
10 = 8 K Byte
11 = 64 K Byte
If the FLA is less than FPBA, then this field reflects the value in the LVSCC.LBES register.
If the FLA is greater or equal to FPBA, then this field reflects the value in the UVSCC.UBES register.
Note: This field is only applicable when in Descriptor mode and Hardware sequencing is being
used.
2 Access Error Log (AEL) — R/W/C. Hardware sets this bit to a 1 when an attempt was made to
access the BIOS region using the direct access method or an access to the BIOS Program Registers
that violated the security restrictions. This bit is simply a log of an access security violation. This bit
is cleared by software writing a 1.
Note: This field is only applicable when in Descriptor mode and Hardware sequencing is being
used.
1 Flash Cycle Error (FCERR) — R/W/C. Hardware sets this bit to 1 when an program register access
is blocked to the FLASH due to one of the protection policies or when any of the programmed cycle
registers is written while a programmed access is already in progress. This bit remains asserted until
cleared by software writing a 1 or until hardware reset occurs due to a global reset or host partition
reset in an Intel ME enabled system. Software must clear this bit before setting the FLASH Cycle GO
bit in this register.
Note: This field is only applicable when in Descriptor mode and Hardware sequencing is being
used.
0 Flash Cycle Done (FDONE) — R/W/C. Intel® Xeon® Processor D-1500 Product Family sets this bit
to 1 when the SPI Cycle completes after software previously set the FGO bit. This bit remains
asserted until cleared by software writing a 1 or hardware reset due to a global reset or host
partition reset in an Intel ME enabled system. When this bit is set and the SPI SMI# Enable bit is set,
an internal signal is asserted to the SMI# generation block. Software must make sure this bit is
cleared prior to enabling the SPI SMI# assertion for a new programmed access.
Note: This field is only applicable when in Descriptor mode and Hardware sequencing is being
used.