Datasheet

Serial Peripheral Interface (SPI)
520 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.1.1 BFPR –BIOS Flash Primary Region Register (SPI Memory
Mapped Configuration Registers)
Memory Address: SPIBAR + 00h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
80h–83h PR3 Flash Protected Range 3 00000000h
84h–87h PR4 Flash Protected Range 4 00000000h
88h–8Fh — Reserved —
90h SSFS Software Sequencing Flash Status 00h
91h–93h SSFC Software Sequencing Flash Control 0000h
94h–95h PREOP Prefix Opcode Configuration 0000h
96h–97h OPTYPE Opcode Type Configuration 0000h
98h–9Fh OPMENU Opcode Menu Configuration 000000000000000
0h
A0h BBAR BIOS Base Address Configuration 00000000h
B0h–B3h FDOC Flash Descriptor Observability Control 00000000h
B4h–B7h FDOD Flash Descriptor Observability Data 00000000h
B8h–C3h — Reserved —
C0h–C3h AFC Additional Flash Control 00000000h
C4h–C7h LVSCC Host Lower Vendor Specific Component Capabilities 00000000h
C8h–C11h UVSCC Host Upper Vendor Specific Component Capabilities 00000000h
D0h–D3h FPB Flash Partition Boundary 00000000h
F0h–F3h SRDL Soft Reset Data Lock 00000000h
F4h–F7h SRDC Soft Reset Data Control 00000000h
F8h–FBh SRD Soft Reset Data 00000000h
Table 15-1. Serial Peripheral Interface (SPI) Register Address Map (SPI Memory Mapped
Configuration Registers) (Sheet 2 of 2)
SPIBAR +
Offset
Mnemonic Register Name Default
Bit Description
31:29 Reserved
28:16 BIOS Flash Primary Region Limit (PRL) — RO. This specifies address bits 24:12 for the Primary
Region Limit.
The value in this register loaded from the contents in the Flash Descriptor.FLREG1.Region Limit
15:13 Reserved
12:0 BIOS Flash Primary Region Base (PRB) — RO. This specifies address bits 24:12 for the Primary
Region Base
The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Base