Datasheet

Functional Description
52 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
If RCTL.PIE is set, an interrupt will be generated. If RCTL.PIE is not set, a message will
be sent to the power management controller so that a GPE can be set. If messages
have been logged (RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, an
interrupt will be generated. This last condition handles the case where the message
was received prior to the operating system re-enabling interrupts after resuming from
a low power state.
3.2.3.4 SMI/SCI Generation
Interrupts for power management events are not supported on legacy operating
systems. To support power management on non-PCI Express aware operating systems,
PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set.
When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/F3/F4/
F5/F6/F7:Offset DCh:Bit 31) to be set.
Additionally, BIOS workarounds for power management can be supported by setting
MPC.PMME (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset D8h:Bit 0). When this bit is set,
power management events will set SMSCS.PMMS (D28:F0/F1/F2/F3/F4/F5/F6/
F7:Offset DCh:Bit 0), and SMI # will be generated. This bit will be set regardless of
whether interrupts or SCI is enabled. The SMI# may occur concurrently with an
interrupt or SCI.
3.2.3.5 Latency Tolerance Reporting (LTR)
The root port supports the extended Latency Tolerance Reporting (LTR) capability. LTR
provides a means for device endpoints to dynamically report their service latency
requirements for memory access to the root port. Endpoint devices should transmit a
new LTR message to the root port each time its latency tolerance changes (and initially
during boot). Intel® Xeon® Processor D-1500 Product Family uses the information to
make better power management decision. The processor uses the worst case tolerance
value communicated by Intel® Xeon® Processor D-1500 Product Family to optimize c-
state transitions. This results in better platform power management without impacting
endpoint functionality.
Note: Endpoint devices the support LTR must implement the reporting and enable mechanism
detailed in the PCIe* Latency Tolerance Reporting Engineering Change Notice.
3.2.4 SERR# Generation
SERR# may be generated using two paths – through PCI mechanisms involving bits in
the PCI header, or through PCI Express* mechanisms involving bits in the PCI Express
capability structure.