Datasheet

High Precision Event Timer Registers
Intel® Xeon® Processor D-1500 Product Family 515
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13:9 Timer n Interrupt Rout (Tn_INT_ROUT_CNF) — R/W / RO. This 5-bit field indicates the
routing for the interrupt to the 8259 or I/O (x) APIC. Software writes to this field to select which
interrupt in the 8259 or I/O (x) will be used for this timer’s interrupt. If the value is not supported
by this particular timer, then the value read back will not match what is written. The software
must only write valid values.
Timer 4, 5, 6, 7: This field is Read Only and reads will return 0.
Notes:
1. If the interrupt is handled using the 8259, only interrupts 0–15 are applicable and valid.
Software must not program any value other than 0–15 in this field.
2. If the Legacy Replacement Rout bit is set, then Timers 0 and 1 will have a different routing,
and this bit field has no effect for those two timers.
3. Timer 0,1: Software is responsible to make sure it programs a valid value (20, 21, 22, or 23)
for this field. Intel® Xeon® Processor D-1500 Product Family logic does not check the
validity of the value written.
4. Timer 2: Software is responsible to make sure it programs a valid value (11, 20, 21, 22, or 23)
for this field. Intel® Xeon® Processor D-1500 Product Family logic does not check the
validity of the value written.
5. Timer 3: Software is responsible to make sure it programs a valid value (12, 20, 21, 22, or 23)
for this field. Intel® Xeon® Processor D-1500 Product Family logic does not check the
validity of the value written.
6. Timers 4, 5, 6, 7: This field is always Read Only 0 as interrupts from these timers can only be
delivered using direct processor interrupt messages.
8 Timer n 32-bit Mode (TIMERn_32MODE_CNF) — R/W or RO. Software can set this bit to force
a 64-bit timer to behave as a 32-bit timer.
Timer 0:Bit is read/write (default to 0). 0 = 64 bit; 1 = 32 bit
Timers 1, 2, 3, 4, 5, 6, 7:Hardwired to 0. Writes have no effect (since these seven timers are 32-
bits).
Note: When this bit is set to 1, the hardware counter will do a 32-bit operation on comparator
match and rollovers; thus, the upper 32-bit of the Timer 0 Comparator Value register is
ignored. The upper 32-bit of the main counter is not involved in any rollover from lower
32-bit of the main counter and becomes all zeros.
7 Reserved. This bit returns 0 when read.
6 Timer n Value Set (TIMERn_VAL_SET_CNF) — R/W. Software uses this bit only for Timer 0 if
it has been set to periodic mode. By writing this bit to a 1, the software is then allowed to directly
set the timer’s accumulator. Software does not have to write this bit back to 1 (it automatically
clears).
Software should not write a 1 to this bit position if the timer is set to non-periodic mode.
Note: This bit will return 0 when read. Writes will only have an effect for Timer 0 if it is set to
periodic mode. Writes will have no effect for Timers 1, 2, 3, 4, 5, 6, 7.
5 Timer n Size (TIMERn_SIZE_CAP) — RO. This read only field indicates the size of the timer.
Timer 0:Value is 1 (64-bits).
Timers 1, 2, 3, 4, 5, 6, 7: Value is 0 (32-bits).
4 Periodic Interrupt Capable (TIMERn_PER_INT_CAP) — RO. If this bit is 1, the hardware
supports a periodic mode for this timer’s interrupt.
Timer 0: Hardwired to 1 (supports the periodic interrupt).
Timers 1, 2, 3, 4, 5, 6, 7: Hardwired to 0 (does not support periodic interrupt).
3 Timer n Type (TIMERn_TYPE_CNF) — R/W or RO.
Timer 0:Bit is read/write. 0 = Disable timer to generate periodic interrupt; 1 = Enable timer to
generate a periodic interrupt.
Timers 1, 2, 3, 4, 5, 6, 7: Hardwired to 0. Writes have no affect.
2 Timer n Interrupt Enable (TIMERn_INT_ENB_CNF) — R/W. This bit must be set to enable
timer n to cause an interrupt when it times out.
0 = Disable (Default). The timer can still count and generate appropriate status bits, but will not
cause an interrupt.
1 = Enable.
Bit Description