Datasheet

High Precision Event Timer Registers
Intel® Xeon® Processor D-1500 Product Family 513
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
14.1.3 GINTR_STA—General Interrupt Status Register
Address Offset: 020h Attribute: R/WC
Default Value: 00000000 00000000h Size: 64 bits
.
1 Legacy Replacement Rout (LEG_RT_CNF) — R/W. If the ENABLE_CNF bit and the LEG_RT_CNF
bit are both set, then the interrupts will be routed as follows:
• Timer 0 is routed to IRQ0 in 8259 or IRQ2 in the I/O APIC
• Timer 1 is routed to IRQ8 in 8259 or IRQ8 in the I/O APIC
• Timer 2-n is routed as per the routing in the timer n config registers.
• If the Legacy Replacement Rout bit is set, the individual routing bits for Timers 0 and 1 (APIC)
will have no impact.
• If the Legacy Replacement Rout bit is not set, the individual routing bits for each of the timers
are used.
• This bit will default to 0. BIOS can set it to 1 to enable the legacy replacement routing, or 0 to
disable the legacy replacement routing.
0 Overall Enable (ENABLE_CNF) — R/W. This bit must be set to enable any of the timers to
generate interrupts. If this bit is 0, then the main counter will halt (will not increment) and no
interrupts will be caused by any of these timers. For level-triggered interrupts, if an interrupt is
pending when the ENABLE_CNF bit is changed from 1 to 0, the interrupt status indications (in the
various Txx_INT_STS bits) will not be cleared. Software must write to the Txx_INT_STS bits to clear
the interrupts.
Note: This bit will default to 0. BIOS can set it to 1 or 0.
Bit Description
Bit Description
63:8 Reserved. These bits will return 0 when read.
7 Timer 7 Interrupt Active (T07_INT_STS) — R/WC. Same functionality as Timer 0.
6 Timer 6 Interrupt Active (T06_INT_STS) — R/WC. Same functionality as Timer 0.
5 Timer 5 Interrupt Active (T05_INT_STS) — R/WC. Same functionality as Timer 0.
4 Timer 4 Interrupt Active (T04_INT_STS) — R/WC. Same functionality as Timer 0.
3 Timer 3 Interrupt Active (T03_INT_STS) — R/WC. Same functionality as Timer 0.
2 Timer 2 Interrupt Active (T02_INT_STS) — R/WC. Same functionality as Timer 0.
1 Timer 1 Interrupt Active (T01_INT_STS) — R/WC. Same functionality as Timer 0.
0 Timer 0 Interrupt Active (T00_INT_STS) — R/WC. The functionality of this bit depends on
whether the edge or level-triggered mode is used for this timer.
(default = 0)
If set to level-triggered mode:
This bit will be set by hardware if the corresponding timer interrupt is active. Once the bit is set, it
can be cleared by software writing a 1 to the same bit position. Writes of 0 to this bit will have no
effect.
If set to edge-triggered mode:
This bit should be ignored by software. Software should always write 0 to this bit.
Note: Defaults to 0. In edge triggered mode, this bit will always read as 0 and writes will have no
effect.