Datasheet
High Precision Event Timer Registers
512 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Notes:
1. Reads to reserved registers or bits will return a value of 0.
2. Software must not attempt locks to the memory-mapped I/O ranges for High Precision Event Timers. If
attempted, the lock is not honored, which means potential deadlock conditions may occur.
14.1.1 GCAP_ID—General Capabilities and Identification Register
Address Offset: 00h Attribute: RO
Default Value: 0429B17F8086A201h Size: 64 bits
14.1.2 GEN_CONF—General Configuration Register
Address Offset: 010h Attribute: R/W
Default Value: 00000000 00000000h Size: 64 bits
160h–167h TIM3_CONG Timer 3 Configuration and Capabilities N/A R/W, RO
168h–16Fh TIM3_COMP Timer 3 Comparator Value N/A R/W
180h–187h TIM4_CONG Timer 4 Configuration and Capabilities N/A R/W, RO
188h–18Fh TIM4_COMP Timer 4 Comparator Value N/A R/W
190h–19Fh — Reserved — —
1A0h–1A7h TIM5_CONG Timer 5 Configuration and Capabilities N/A R/W, RO
1A8h–1AFh TIM5_COMP Timer 5 Comparator Value N/A R/W
1B0h–1BFh — Reserved — —
1C0h–1C7h TIM6_CONG Timer 6 Configuration and Capabilities N/A R/W, RO
1C8h–1CFh TIM6_COMP Timer 6 Comparator Value N/A R/W
1D0h–1DFh — Reserved — —
1E0h–1E7h TIM7_CONG Timer 7 Configuration and Capabilities N/A R/W, RO
1E8h–1EFh TIM7_COMP Timer 7 Comparator Value N/A R/W
1F0h–19Fh — Reserved — —
200h–3FFh — Reserved — —
Table 14-1. Memory-Mapped Register Address Map (Sheet 2 of 2)
Offset Mnemonic Register Default Attribute
Bit Description
63:32 Main Counter Tick Period (COUNTER_CLK_PER_CAP) — RO. This field indicates the period at which
the counter increments in femptoseconds (10^-15 seconds). This will return 0429B17Fh when
read. This indicates a period of 69841279 fs (69.841279 ns).
31:16 Vendor ID Capability (VENDOR_ID_CAP) — RO. This is a 16-bit value assigned to Intel.
15 Legacy Replacement Rout Capable (LEG_RT_CAP) — RO. Hardwired to 1. Legacy Replacement
Interrupt Rout option is supported.
14 Reserved. This bit returns 0 when read.
13 Counter Size Capability (COUNT_SIZE_CAP) — RO. Hardwired to 1. Counter is 64-bit wide.
12:8 Number of Timer Capability (NUM_TIM_CAP) — RO. This field indicates the number of timers in
this block.
07h = Eight timers.
7:0 Revision Identification (REV_ID) — RO. This indicates which revision of the function is
implemented. Default value will be 01h.
Bit Description
63:2 Reserved. These bits return 0 when read.