Datasheet
High Precision Event Timer Registers
Intel® Xeon® Processor D-1500 Product Family 511
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
14 High Precision Event Timer
Registers
The timer registers are memory-mapped in a non-indexed scheme. This allows the
processor to directly access each register without having to use an index register. The
timer register space is 1024 bytes. The registers are generally aligned on 64-bit
boundaries to simplify implementation with IA64 processors. There are four possible
memory address ranges beginning at 1) FED0_0000h, 2) FED0_1000h, 3)
FED0_2000h, 4) FED0_3000h. The choice of address range will be selected by
configuration bits in the High Precision Timer Configuration Register (Chipset Config
Registers:Offset 3404h).
Behavioral Rules:
1. Software must not attempt to read or write across register boundaries. For
example, a 32-bit access should be to offset x0h, x4h, x8h, or xCh. 32-bit accesses
should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh, 0Eh, or 0Fh.
Any accesses to these offsets will result in an unexpected behavior, and may result
in a master abort. However, these accesses should not result in system hangs.
64-bit accesses can only be to x0h and must not cross 64-bit boundaries.
2. Software should not write to Read Only registers.
3. Software should not expect any particular or consistent value when reading
reserved registers or bits.
14.1 Memory Mapped Registers
Table 14-1. Memory-Mapped Register Address Map (Sheet 1 of 2)
Offset Mnemonic Register Default Attribute
000h–007h GCAP_ID General Capabilities and Identification 0429B17F8086
A201h
RO
008h–00Fh — Reserved — —
010h–017h GEN_CONF General Configuration 000000000000
0000h
R/W
018h–01Fh — Reserved — —
020h–027h GINTR_STA General Interrupt Status 000000000000
0000h
R/WC
028h–0EFh — Reserved — —
0F0h–0F7h MAIN_CNT Main Counter Value N/A R/W
0F8h–0FFh — Reserved — —
100h–107h TIM0_CONF Timer 0 Configuration and Capabilities N/A R/W, RO
108h–10Fh TIM0_COMP Timer 0 Comparator Value N/A R/W
110h–11Fh — Reserved — —
120h–127h TIM1_CONF Timer 1 Configuration and Capabilities N/A R/W, RO
128h–12Fh TIM1_COMP Timer 1 Comparator Value N/A R/W
130h–13Fh — Reserved — —
140h–147h TIM2_CONF Timer 2 Configuration and Capabilities N/A R/W, RO
148h–14Fh TIM2_COMP Timer 2 Comparator Value N/A R/W
150h–15Fh — Reserved — —