Datasheet

PCI Express* Configuration Registers

Intel® Xeon® Processor D-1500 Product Family 509

Datasheet - Volume 1 of 4: Integrated Platform Controller Hub

March 2015

13.1.62 PEETM—PCI Express* Extended Test Mode Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)

Address Offset: 324h–327h Attribute: RO

Default Value: See Description Size: 32 bits

13.1.63 PEC1—PCI Express* Configuration Register 1

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)

Address Offset: 330h–333h Attribute: RO, R/W

Default Value: 28000016h Size: 32 bits

21 PECR2 Field 1 — R/W. BIOS must set this bit to 1b.

20:0 Reserved

Bit Description

31:5 Reserved

4 Lane Reversal (LR) — RO.

This register reads the setting of the PCIELR1 soft strap for port 1 and the PCIELR2 soft strap for port

0 = No Lane reversal (default).

1 = PCI Express lanes 0-3 (register in port 1) or lanes 4-7 (register in port 5) are reversed.

Notes:

1. The port configuration straps must be set such that Port 1 or Port 5 is configured as a x4 port

using lanes 0–3, or 4–7 when Lane Reversal is enabled. x2 lane reversal is not supported.

2. This register is only valid on port 1 (for ports 1–4) or port 5 (for ports 5–8).

3 Reserved

2 Scrambler Bypass Mode (BAU) — R/W.

0 = Normal operation. Scrambler and descrambler are used.

1 = Bypasses the data scrambler in the transmit direction and the data de-scrambler in the receive

direction.

Note: This functionality intended for debug/testing only.

Note: If bypassing scrambler with Intel® Xeon® Processor D-1500 Product Family root port 1 in

x4 configuration, each Intel® Xeon® Processor D-1500 Product Family root port must have

this bit set.

1:0 Reserved

Bit Description

31:8 Reserved

7:0 PEC1 Field 1 — R/W. BIOS must program this field to 40h.