Datasheet

PCI Express* Configuration Registers
508 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.59 AECC—Advanced Error Capabilities and Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 118h–11Bh Attribute: RO
Default Value: 00000000h Size: 32 bits
13.1.60 RES—Root Error Status Register (PCI Express*—D28:F0/
F1/F2/F3/F4/F5/F6/F7)
Address Offset: 130h–133h Attribute: R/WC, RO
Default Value: 00000000h Size: 32 bits
13.1.61 PECR2—PCI Express* Configuration Register 2
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 320–323h Attribute: R/W
Default Value: 0004B05Bh Size: 32 bits
5:1 Reserved
0 Receiver Error Mask (RE) — R/WO. Mask for receiver errors.
Bit Description
Bit Description
31:9 Reserved
8 ECRC Check Enable (ECE) — RO. ECRC is not supported.
7 ECRC Check Capable (ECC) — RO. ECRC is not supported.
6 ECRC Generation Enable (EGE) — RO. ECRC is not supported.
5 ECRC Generation Capable (EGC) — RO. ECRC is not supported.
4:0 First Error Pointer (FEP) — RO. Identifies the bit position of the last error reported in the
Uncorrectable Error Status Register.
Bit Description
31:27 Advanced Error Interrupt Message Number (AEMN) — RO. There is only one error interrupt
allocated.
26:7 Reserved
6 Fatal Error Messages Received (FEMR) — RO. Set when one or more Fatal Uncorrectable Error
Messages have been received.
5 Non-Fatal Error Messages Received (NFEMR)— RO. Set when one or more Non-Fatal
Uncorrectable error messages have been received
4 First Uncorrectable Fatal (FUF)— RO. Set when the first Uncorrectable Error message received is
for a fatal error.
3 Multiple ERR_FATAL/NONFATAL Received (MENR) — RO. For Intel® Xeon® Processor D-1500
Product Family , only one error will be captured.
2 ERR_FATAL/NONFATAL Received (ENR) — R/WC.
0 = No error message received.
1 = Either a fatal or a non-fatal error message is received.
1 Multiple ERR_COR Received (MCR) — RO. For Intel® Xeon® Processor D-1500 Product Family ,
only one error will be captured.
0 ERR_COR Received (CR) — R/WC.
0 = No error message received.
1 = A correctable error message is received.
Bit Description
31:20 Reserved