Datasheet

PCI Express* Configuration Registers
506 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.56 UEV—Uncorrectable Error Severity Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 10Ch–10Fh Attribute: RO, R/W
Default Value: 00060011h Size: 32 bits
20 Unsupported Request Error Mask (URE) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked.
19 ECRC Error Mask (EE) — RO. ECRC is not supported.
18 Malformed TLP Mask (MT) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked.
17 Receiver Overflow Mask (RO) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked.
16 Unexpected Completion Mask (UC) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked.
15 Completion Abort Mask (CA) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked.
14 Completion Timeout Mask (CT) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked.
13 Flow Control Protocol Error Mask (FCPE) — RO. Flow Control Protocol Errors not supported.
12 Poisoned TLP Mask (PT) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked.
11:5 Reserved
4 Data Link Protocol Error Mask (DLPE) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked.
3:1 Reserved
0 Training Error Mask (TE) — RO. Training Errors not supported
Bit Description
Bit Description
31:21 Reserved
20 Unsupported Request Error Severity (URE) — R/W.
0 = Error considered non-fatal. (Default)
1 = Error is fatal.
19 ECRC Error Severity (EE) — RO. ECRC is not supported.
18 Malformed TLP Severity (MT) — R/W.
0 = Error considered non-fatal.
1 = Error is fatal. (Default)
17 Receiver Overflow Severity (RO) — R/W.
0 = Error considered non-fatal.
1 = Error is fatal. (Default)
16 Reserved
15 Completion Abort Severity (CA) — R/W.
0 = Error considered non-fatal. (Default)
1 = Error is fatal.
14 Reserved
13 Flow Control Protocol Error Severity (FCPE) — RO. Flow Control Protocol Errors not supported.