Datasheet

PCI Express* Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 505
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.54 UES—Uncorrectable Error Status Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 104h–107h Attribute: R/WC, RO
Default Value: 00000000000x0xxx0x0x0000000x0000b
Size: 32 bits
This register maintains its state through a platform reset. It loses its state upon
suspend.
13.1.55 UEM—Uncorrectable Error Mask Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 108h–10Bh Attribute: R/WO, RO
Default Value: 00000000h Size: 32 bits
When set, the corresponding error in the UES register is masked, and the logged error
will cause no action. When cleared, the corresponding error is enabled.
1 Subtractive Decode Compatibility Device ID (SDCDID) — R/W.
0 = This function reports the device Device ID value assigned to the PCI Express Root Ports.
1 = This function reports a Device ID of 244Eh.
If subtractive decode (SDE) is enabled, having this bit as '0' allows the function to present a
Device ID that is recognized by the operating system.
0 Subtractive Decode Enable (SDE) — R/W.
0 = Subtractive decode is disabled this function and will only claim transactions positively.
1 = This port will subtractively forward transactions across the PCIe link downstream memory
and IO transactions that are not positively claimed any internal device or bridge.
Software must ensure that only one Intel® Xeon® Processor D-1500 Product Family device is
enabled for Subtractive decode at a time.
Bit Description
Bit Description
31:21 Reserved
20 Unsupported Request Error Status (URE) — R/WC. Indicates an unsupported request was
received.
19 ECRC Error Status (EE) — RO. ECRC is not supported.
18 Malformed TLP Status (MT) — R/WC. Indicates a malformed TLP was received.
17 Receiver Overflow Status (RO) — R/WC. Indicates a receiver overflow occurred.
16 Unexpected Completion Status (UC) — R/WC. Indicates an unexpected completion was received.
15 Completion Abort Status (CA) — R/WC. Indicates a completer abort was received.
14 Completion Timeout Status (CT) — R/WC. Indicates a completion timed out. This bit is set if
Completion Timeout is enabled and a completion is not returned within the time specified by the
Completion TImeout Value
13 Flow Control Protocol Error Status (FCPE) — RO. Flow Control Protocol Errors not supported.
12 Poisoned TLP Status (PT) — R/WC. Indicates a poisoned TLP was received.
11:5 Reserved
4 Data Link Protocol Error Status (DLPE) — R/WC. Indicates a data link protocol error occurred.
3:1 Reserved
0 Training Error Status (TE) — RO. Training Errors not supported.
Bit Description
31:21 Reserved