Datasheet

PCI Express* Configuration Registers
504 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.51 SMSCS—SMI/SCI Status Register (PCI Express*—D28:F0/
F1/F2/F3/F4/F5/F6/F7)
Address Offset: DCh–DFh Attribute: R/WC
Default Value: 00000000h Size: 32 bits
13.1.52 RPDCGEN—Root Port Dynamic Clock Gating Enable
Register (PCI Express—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: E1h Attribute: R/W
Default Value: 00h Size: 8-bits
13.1.53 PECR3—PCI Express* Configuration Register 3
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: ECh–EFh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31 Power Management SCI Status (PMCS) — R/WC.
1 = PME control logic needs to generate an interrupt, and this interrupt has been routed to generate
an SCI.
30 Hot-Plug SCI Status (HPCS) — R/WC.
1 = Hot-Plug controller needs to generate an interrupt, and has this interrupt been routed to
generate an SCI.
29:5 Reserved
4 Hot-Plug Link Active State Changed SMI Status (HPLAS) — R/WC.
1 = SLSTS.LASC (D28:F0/F1/F2/F3/F4/F5/F6/F7:5Ah, bit 8) transitioned from 0-to-1, and
MPC.HPME (D28:F0/F1/F2/F3/F4/F5/F6/F7:D8h, bit 1) is set. When this bit is set, an SMI# will
be generated.
3:2 Reserved
1 Hot-Plug Presence Detect SMI Status (HPPDM) — R/WC.
1 = SLSTS.PDC (D28:F0/F1/F2/F3/F4/F5/F6/F7:5Ah, bit 3) transitioned from 0-to-1, and MPC.HPME
(D28:F0/F1/F2/F3/F4/F5/F6/F7:D8h, bit 1) is set. When this bit is set, an SMI# will be
generated.
0 Power Management SMI Status (PMMS) — R/WC.
1 = RSTS.PS (D28:F0/F1/F2/F3/F4/F5/F6/F7:60h, bit 16) transitioned from 0-to-1, and MPC.PMME
(D28:F0/F1/F2/F3/F4/F5/F6/F7:D8h, bit 1) is set.
Bits Description
7:4 Reserved. RO
3 Shared Resource Dynamic Link Clock Gating Enable (SRDLCGEN) — R/W.
0 = Disables dynamic clock gating of the shared resource link clock domain.
1 = Enables dynamic clock gating on the root port shared resource link clock domain.
Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for ports 5–8.
2 Shared Resource Dynamic Backbone Clock Gate Enable (SRdBCGEN) — R/W.
0 = Disables dynamic clock gating of the shared resource backbone clock domain.
1 = Enables dynamic clock gating on the root port shared resource backbone clock domain.
Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for ports 5–8.
1 Root Port Dynamic Link Clock Gate Enable (RPDLCGEN) — R/W.
0 = Disables dynamic clock gating of the root port link clock domain.
1 = Enables dynamic clock gating on the root port link clock domain.
0 Root Port Dynamic Backbone Clock Gate Enable (RPdBCGEN) — R/W.
0 = Disables dynamic clock gating of the root port backbone clock domain.
1 = Enables dynamic clock gating on the root port backbone clock domain.
Bit Description
31:2 Reserved