Datasheet

PCI Express* Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 503
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
24 BME Receive Check Enable (BMERCE) — R/W. When set, the receive transaction layer will treat
the TLP as an Unsupported Request error if a memory read or write request is received and the Bus
Master Enable bit is not set.
Messages, I/O, Config, and Completions are never checked for BME.
23 Reserved
22 Detect Override (FORCEDET) — R/W.
0 = Normal operation. Detected output from AFE is sampled for presence detection.
1 = Override mode. Ignores AFE detect output and link training proceeds as if a device were
detected.
21 Flow Control During L1 Entry (FCDL1E) — R/W.
0 = No flow control update DLLPs sent during L1 Ack transmission.
1 = Flow control update DLLPs sent during L1 Ack transmission as required to meet the 30 μs
periodic flow control update.
20:18 Unique Clock Exit Latency (UCEL) — R/W. This value represents the L0s Exit Latency for unique-
clock configurations (LCTL.CCC = 0) (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 50h:bit 6). It defaults to
512 ns to less than 1 µs, but may be overridden by BIOS.
17:15 Common Clock Exit Latency (CCEL) — R/W. This value represents the L0s Exit Latency for
common-clock configurations (LCTL.CCC = 1) (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 50h:bit 6). It
defaults to 128 ns to less than 256 ns, but may be overridden by BIOS.
14 PCIe Gen2 Speed Disable — R/W.
0 = PCIe supported data rate is defined as set through Supported Link Speed and Target Link Speed
settings.
1 = PCIe supported data rate is limited to 2.5 GT/s (Gen1). Supported Link Speed register bits will
reflect “0001b” when this bit is set.
When this bit is changed, link retrain needs to be performed for the change to be effective.
13:8 Reserved
7 Port I/OxAPIC Enable (PAE) — R/W.
0 = Hole is disabled.
1 = A range is opened through the bridge for the following memory addresses:
6:3 Reserved
2 Bridge Type (BT) — R/WO. This register can be used to modify the Base Class and Header Type
fields from the default PCI-to-PCI bridge to a Host Bridge. Having the root port appear as a Host
Bridge is useful in some server configurations.
0 = The root port bridge type is a PCI-to-PCI Bridge, Header Sub-Class = 04h, and Header Type =
Typ e 1 .
1 = The root port bridge type is a PCI-to-PCI Bridge, Header Sub-Class = 00h, and Header Type =
Typ e 0 .
1 Hot-Plug SMI Enable (HPME) — R/W.
0 = SMI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SMI whenever a Hot-Plug event is detected.
0 Power Management SMI Enable (PMME) — R/W.
0 = SMI generation based on a power management event is disabled.
1 = Enables the root port to generate SMI whenever a power management event is detected.
Bit Description
Port # Address
1 FEC1_0000h – FEC1_7FFFh
2 FEC1_8000h – FEC1_FFFFh
3 FEC2_0000h – FEC2_7FFFh
4 FEC2_8000h – FEC2_FFFFh
5 FEC3_0000h – FEC3_7FFFh
6 FEC3_8000h – FEC3_FFFFh
7 FEC4_0000h – FEC4_7FFFh
8 FEC4_8000h – FEC4_FFFFh