Datasheet

PCI Express* Configuration Registers
502 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.49 MPC2—Miscellaneous Port Configuration Register 2
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: D4h–D7h Attribute: R/W, RO
Default Value: 00000800h Size: 32 bits
13.1.50 MPC—Miscellaneous Port Configuration Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: D8h–dBh Attribute: R/W, RO, R/WO
Default Value: 09110000h Size: 32 bits
Bit Description
31:5 Reserved
4 ASPM Control Override Enable (ASPMCOEN) — R/W.
1 = Root port will use the values in the ASPM Control Override registers
0 = Root port will use the ASPM Registers in the Link Control register.
Notes: This register allows BIOS to control the root port ASPM settings instead of the OS.
3:2 ASPM Control Override (ASPMO) — R/W. Provides BIOS control of whether root port should
enter L0s or L1 or both.
00 = Disabled
01 = L0s Entry Enabled
10 = L1 Entry Enabled
11 = L0s and L1 Entry Enabled.
1 EOI Forwarding Disable (EOIFD) — R/W. When set, EOI messages are not claimed on the
backbone by this port an will not be forwarded across the PCIe link.
0 = Broadcast EOI messages that are sent on the backbone are claimed by this port and
forwarded across the PCIe* link.
1 = Broadcast EOI messages are not claimed on the backbone by this port and will not be
forwarded across the PCIe Link.
0 L1 Completion Timeout Mode (LICTM) — R/W.
0 = PCI Express Specification Compliant. Completion timeout is disabled during software
initiated L1, and enabled during ASPM initiate L1.
1 = Completion timeout is enabled during L1, regardless of how L1 entry was initiated.
Bit Description
31 Power Management SCI Enable (PMCE) — R/W.
0 = SCI generation based on a power management event is disabled.
1 = Enables the root port to generate SCI whenever a power management event is detected.
30 Hot-Plug SCI Enable (HPCE) — R/W.
0 = SCI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SCI whenever a Hot-Plug event is detected.
29 Link Hold Off (LHO) — R/W.
1 = Port will not take any TLP. This is used during loopback mode to fill up the downstream queue.
28 Address Translator Enable (ATE) — R/W. This bit is used to enable address translation using the
AT bits in this register during loopback mode.
0 = Disable
1 = Enable
27 Reserved
26 Invalid Receive Bus Number Check Enable (IRBNCE) — R/W. When set, the receive transaction
layer will signal an error if the bus number of a Memory request does not fall within the range
between SCBN and SBBN. If this check is enabled and the request is a memory write, it is treated as
an Unsupported Request. If this check is enabled and the request is a non-posted memory read
request, the request is considered a Malformed TLP and a fatal error.
Messages, I/O, Config, and Completions are never checked for valid bus number.
25 Invalid Receive Range Check Enable (IRRCE) — R/W. When set, the receive transaction layer
will treat the TLP as an Unsupported Request error if the address range of a Memory request does
not outside the range between prefetchable and non-prefetchable base and limit.
Messages, I/O, Configuration, and Completions are never checked for valid address ranges.