Datasheet

PCI Express* Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 501
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.47 PMC—PCI Power Management Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: A2h–A3h Attribute: RO
Default Value: C803h Size: 16 bits
13.1.48 PMCS—PCI Power Management Control and Status
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: A4h–A7h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
15:11 PME_Support (PMES) — RO. Indicates PME# is supported for states D0, D3
HOT
and D3
COLD
. The
root port does not generate PME#, but reporting that it does is necessary for some legacy operating
systems to enable PME# in devices connected behind this root port.
10 D2_Support (D2S) — RO. The D2 state is not supported.
9 D1_Support (D1S) — RO The D1 state is not supported.
8:6 Aux_Current (AC) — RO. Reports 375 mA maximum suspend well current required when in the
D3
COLD
state.
5 Device Specific Initialization (DSI) — RO.
1 = Indicates that no device-specific initialization is required.
4Reserved
3 PME Clock (PMEC) — RO.
1 = Indicates that PCI clock is not required to generate PME#.
2:0 Version (VS) — RO. Indicates support for Revision 1.2 of the PCI Power Management Specification.
Bit Description
31:24 Reserved
23 Bus Power / Clock Control Enable (BPCE) — Reserved per PCI Express* Base Specification, Revision
1.0a.
22 B2/B3 Support (B23S) — Reserved per PCI Express* Base Specification, Revision 1.0a.
21:16 Reserved
15 PME Status (PMES) — RO.
1 = Indicates a PME was received on the downstream link.
14:9 Reserved
8 PME Enable (PMEE) — R/W.
1 = Indicates PME is enabled. The root port takes no action on this bit, but it must be R/W for some
legacy operating systems to enable PME# on devices connected to this root port.
This bit is sticky and resides in the resume well. The reset for this bit is RSMRST# which is not
asserted during a warm reset.
7:2 Reserved
1:0 Power State (PS) — R/W. This field is used both to determine the current power state of the root
port and to set a new power state. The values are:
00 = D0 state
11 = D3
HOT
state
Note: When in the D3
HOT
state, the controller’s configuration space is available, but the I/O and
memory spaces are not. Type 1 configuration cycles are also not accepted. Interrupts are
not required to be blocked as software will disable interrupts prior to placing the port into
D3HOT. If software attempts to write a ‘10’ or ‘01’ to these bits, the write will be ignored.